Xilinx simulator errors: port size does not match connection size

# ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) C:/Xilinx/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i /gtp_dual_swift_1
# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.
# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport
# Runtime, SwiftPLI v1.13

trn_tbuf_av[2]

Contact modelsim/XIlinx. I guess related to PCIE core simulation library.

vsim-3015

The width of the regs/wires that you have used to connect to the ports of the listed modules are incorrect.

For example, one warning is telling you that port trn_tbuf_av is 5 bits wide and you have connected to a 3-bit bus.

Review your connections for the listed modules.

r.b.