Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

WHy we use NAND gate only in CMOS than NOR gate

Status
Not open for further replies.
R

ravi for VLSI

Newbie level 1
Joined
Dec 16, 2007
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,292
why use nand gate than nor

I have a doubt here.Even we can design any ckt using either NAND and NOR gate.why NAND gate is used more.Pls give me answer in detail .i am at begining stage.
with regards,
Ravi.
 

why we use nand gate

NAND have equal rise and fall times..that why its faster
 

A two input NOR has two PMOS in series... hence it occupies more area to have good rise and fall times...so NAND is preffered than NOR...
 

NAND will have less leakage current than NOR while implementing in CMOS.
 

from point of logic effort ,NAND is faster than NOR ,and easy be driven

Added after 1 minutes:

r/f time ,both of them can be balanced.
 

chandooo said:
NAND will have less leakage current than NOR while implementing in CMOS.
Click to expand...

Hi chandoo...
is it so that NAND has less leakage current...? how is this...? can you explain the phenomenon....
 

NMOS transistors are ON for the most of the NOR operations, so the leakage power. Refer the attachment for more details.
 

is that why we use sleep(shut down) PMOS?
PMOS is better than NMOS in leakage power?(same size)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top