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about the rise/fall time of the clk

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spring1860

spring1860

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hi
i have a question of the rise/fall time of the CLK in switching capacitor ckts, for example , for a 40MHz clk, how many rise/fall time is best , is there any criteria?
thx a lot .
 

there is only consideration about the EMC.

for the design, you can ignore it.
 

Well, it also impacts charge injection (if the clock is very slow).
 

it also will impact the IR drop
 

lladnar23 said:
Well, it also impacts charge injection (if the clock is very slow).
Click to expand...

do you mean if the clock is very slow ,the charge injectioin will become very serious?

thx .

Added after 3 minutes:

lovexxnu said:
it also will impact the IR drop
Click to expand...

would u pls explain it in details , how it impact the IR drop ?

:cry:
 

do you have some material about EMC considerations in IC design?
 

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