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why a non-standard 6 layer stackup?

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Nails

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de1 sdram 100mhz

Hi,

I am trying to analyze the layout and construction of an Altera DE1 development board, because I want to make a board similar to it.

I have determined that it is a 6 layer board with the following layer stackup based upon grinding down the side of the board to reveal the copper layers, and probing to know VCC and GND signal test points. Details on inner layers were gleaned by trying to route an idential circuit from the assigned FPGA pins to the SRAM, and using the same via's and placement of the SDRAM.

1 - signals
2 - signals (always only crossing layer 1 signals at a 45 or 90 degree angle, never in parallel)
3 - gnd
(large core here between gnd and vcc)
4 - vcc
5 - signals (only a few)
6 - mainly a gnd plane, but a few signals are routed into it.

However, upon reading almost everything I can about layer stackups, this is a stackup that is rarely recommended. The most common one is:

1 - signals
2 - gnd
3 - signals
(large core here)
4 - signals
5 - vcc
6 - signals

Using this method seems much more preferable as you don't have the problem of running traces on signal layers 1 & 2 at an angle to each other. Also, high speed signals and clocks can be on inner layers and shielded.

So what would be the advantage to constructing the board the first way and have to go through extra routing trouble to avoid cross-talk in signals on layers 1 and 2? Is this advantage a big deal?

I am stumped...I actually found one board reference design that suggested to lay things out this first way, but I can not find it now. 99% of all other reference designs say to do the layer stackup the second way.

Does it really matter when you are only running around 100 Mhz?

The only thing I can think of is there might be some manufacturability reasons because of the numerous tiny via holes. ???

Any insight would be greatly appreciated.

Thanks.
 

6 layer board stack-ups

It's just a matter of designer preference. You are correct that the second stackup would normally be the desired method.

My guess would be that the designer restricted his critical signals to layers 5 and 6. The remainder of the layers are used for less critical routing.

Apparently, there aren't very many controlled impedance traces. I wouldn't have designed the board as described. I would have used the more conventional stackup. Maybe they gave the project to some junior designer, and he just got lucky that everything worked - it happens.
 

vcc gnd 6-layer pcb

There are no "real" high speed on DE1 board and I don't think who did this board were thinking about stack up.


For your board think about what kind of BGA package you will select, what is highest frequency will be on the board, Do you need to do the emission testing and etc...

For same configuration as DE1 board I will do 8 layers PCB and keep everything close to FPGA, also decoupling capacitors should be on the bottom of the board, not few inches away from the chip
 

8l stack-up reference design

Nails said:
Hi,

I am trying to analyze the layout and construction of an @ltera DE1 development board, because I want to make a board similar to it.

I have determined that it is a 6 layer board with the following layer stackup based upon grinding down the side of the board to reveal the copper layers, and probing to know VCC and GND signal test points. Details on inner layers were gleaned by trying to route an idential circuit from the assigned FPGA pins to the SRAM, and using the same via's and placement of the SDRAM.

1 - signals
2 - signals (always only crossing layer 1 signals at a 45 or 90 degree angle, never in parallel)
3 - gnd
(large core here between gnd and vcc)
4 - vcc
5 - signals (only a few)
6 - mainly a gnd plane, but a few signals are routed into it.

However, upon reading almost everything I can about layer stackups, this is a stackup that is rarely recommended. The most common one is:

1 - signals
2 - gnd
3 - signals
(large core here)
4 - signals
5 - vcc
6 - signals

Definitely this is not "the most common", just one choice.
It has problems with the inequal noise level on gnd and vcc, and thus those problems are translated on all signal layers.
There are no real stripline layers (just microstrip), so fast differential signals could be routed only on layer3 (assuming the rule of don't routing too much on top and bottom is known)
Rejecting noise by using ZBC layers is impossible on this arrangement.

And BTW, there is no essential cost difference between 6 layers and 8 layers, so why 6 ?



Using this method seems much more preferable as you don't have the problem of running traces on signal layers 1 & 2 at an angle to each other. Also, high speed signals and clocks can be on inner layers and shielded.

So what would be the advantage to constructing the board the first way and have to go through extra routing trouble to avoid cross-talk in signals on layers 1 and 2? Is this advantage a big deal?

I am stumped...I actually found one board reference design that suggested to lay things out this first way, but I can not find it now. 99% of all other reference designs say to do the layer stackup the second way.

Does it really matter when you are only running around 100 Mhz?

The only thing I can think of is there might be some manufacturability reasons because of the numerous tiny via holes. ???

Any insight would be greatly appreciated.

Thanks.
Click to expand...
 

six layer stackup

NAILS - the stackup depends on many things. Sometimes power distribution is an issue. If you cannot place decoupling capacitors near the chips. If you have EMC issues, etc. In such a case it is often needed to place the VCC and GND layers as close to each other as possible. This will minimize the inductance of the planes and the capacitor placement is much less critical.
100MHz in some cases is viewed upon as high frequency. Most likely you can get away with any layout quality without serious signal integrity questions, but poor layout will cause EMC problems even @100MHz.
PCB designers in the past used to use routing layers to move traces in one direction only (now good tools and higher freq. signals have somewhat decreased that trend). This is the quickest and easiest way to route high density, if the speed is relatively low and adding vias is not a problem. So this is not merely a question of crosstalk, but also a trade trick of layout people to minimize layout time.

MELC - you are almost right there... But I must point out that in most cases VCC and GND layers should look similar from the impedance point of view. So, provided that VCC is a full plane, you can route the controlled impedance striplines also over that.
 

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