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variable l1 : line;
variable var1 : std_logic_vector(7 downto 0);
.
.
readline(f1,l1); --read a line from a file f1 which contains hex words example FE
hread(var1,l1); -- read into var1, a hex value from line l1.
variable l1 : line;
variable var1 : std_logic_vector(7 downto 0);
variable var_five_bits : std_logic(4 downto 0);
.
.
readline(f1,l1); --read a line from a file which contains hex words example FE
hread(var1,l1);
var_five_bits := var1(4 downto 0);
shenql said:if i want to get the mid 4bits .can i get this
signal xx : std_logic_vector (7 downto 0);
signal mid4bites: std_logic_vector (3 downto 0);
mid4bits<=xx(5 downto 2);
?
cfriend said:do you want to translate hex into binary in VHDL fomat?
such as assembler -> hex file -> binary in VHDL format, and then run the code in FPGA or CPLD use for debuging your microprocessor which is implemented in FPGA or CPLD??
Added after 1 minutes:
I used one c code transfer hex into verilog format, in my opinion, it is the same as VHDL