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Over voltage protection in LDO

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tia_design

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ldo vishal gupta

I plan to design a LDO using CMOS process. The maximum voltage for this process is 9V. The LDO will be protected from 18V maximum transient voltage.
There is no Zener diode and NPN device in this process. Can any one give me some good idea for high voltage protection? Thanks!
 

use the inverse aspect of ldo

and use two ldo to form a current mirror
this way overvoltage in = null current from any imbalance...

to form a BRIDGED LDOR
 

Hi, VSMVDD,

Thanks a lot for your reply. Can you give a little more detailed description of your idea? My process is dual well nwell, if there are two LDO, I think the mos devices in one of the LDO will experience overvoltage probelm.

By the way, is your idea similar to the following paper:
A Low Dropout, CMOS Regulator with High PSR over Wideband Frequencis by Vishal Gupta
 

What's max current output for your LDO?
If it is not too high, you can try series a resistor and some voltage clamp to realize it. Otherwise, I think it is mission impossible.
 

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