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Doubt regarding VHDL 9-value logic application in Xilinx FPGA

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vlsi_freak

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Hi.

I have a doubt regarding VHDL 9 value logic application in Xilinx FPGA. Its is said that there are 9- logic values which can be used while writing HDL's but in most of the designs i can see obly logic 0, logic 1 and 'Z' (High Impedence).

I am writing a code for Spartan FPGA's.

My question is, what is the use of Weak Unknown(W), Weak zero (L), Weak High (H), while writing a code in VHDL. Is there anything like i can enable Pull up, Pull down in FPGA's with the help of these.

Regards

Added after 3 hours 31 minutes:

Added after 48 seconds:

Hi..


Can anyone help me out!!!

Thanks
 

Re: VHDL 9-value logic

In VHDL, we always have U and L and H (not sure about W, maybe it's U??). It's for pullup and pulllow in tristate purpose. I don't think it can be synthesized.




vlsi_freak said:
Hi.

I have a doubt regarding VHDL 9 value logic application in Xilinx FPGA. Its is said that there are 9- logic values which can be used while writing HDL's but in most of the designs i can see obly logic 0, logic 1 and 'Z' (High Impedence).

I am writing a code for Spartan FPGA's.

My question is, what is the use of Weak Unknown(W), Weak zero (L), Weak High (H), while writing a code in VHDL. Is there anything like i can enable Pull up, Pull down in FPGA's with the help of these.

Regards

Added after 3 hours 31 minutes:

Added after 48 seconds:

Hi..


Can anyone help me out!!!

Thanks
Click to expand...

Added after 1 minutes:

For Xilinx FPGA pullup and pulllow, I think you can use pad constrain...

You may use H, L, U in testbench design
 

Re: VHDL 9-value logic

Hi vlsi_freak!
yes u'r right weak high or low value r used for modelling pull-ups. for example:
u've a signal line which u want to keep in either high or low logic value (when no-one is driving that line), then u can give it value either weak high or low accordingly so that when someone starts driving that signal no error or signal-contention occurs on that line (sine weak high or low will always get over-ride by that driving value). On the other hand if u assign it strong high or low value then signal-contention (or unknown value) will occur if the driver tries to drive it with other logic value.
 

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