Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
a cmos circuit is constructed with pmos in pullup and nmos in pulldown operation.at any point of time in circuit operation both pmos and nmos are never in on state.only either pmos or nmos is in on state.so there is no shortcircuit path from VDD to GNd during operation .so there is no point of shortcircuit power consumption.that is why cmos circuit consumes low power
If it is not going to happen then why we are saying that
Bfore nmos is on pmos will also gets on so there will be a short circuit power dissipation...
I think its not going to happen practically am i right?
Reply me
Bye take care
No doubts about it. Definitely both the devices will be on But the time for which they get on simultaneously is ver y very small, hundredth of second or even less (depends on many factors). When compared to other families, it is almost negligible. For this reason, its known as low power device.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
