jerry2007
Newbie level 5
I am trying to use clk as the selector of a mux at the end of the design to select b/w two outputs alternatively to achieve higher freq outputs. But the skew between clk and inverted clk (clk_inv) is so large that it causes a big glitch in the output. My question is how to specify this timing constraint in the SDC file (or somewhere else?) to let the tool make some effort to synchonize these two signals?
Thanks in advance!
Thanks in advance!