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Timing of Static CMOS logic vs Domino CMOS

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gliss

gliss

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static domino cmos

How would you compare the the timing of a gate implemented using Static CMOS vs the timing of a gate using Domino Logic? Domino Logic is like Dynamic CMOS logic but with the inclusion of a static inverter on the output.
The timing comparison is not easy because Static doesn't use a clock while Domino does.
 

Well, I wont compare delays at the gate level if I am using Domino logic: I would then compare the frequency at which a block operates, and of course the through put of the block with and without Domino logic.
As you might have heard that ARM is now using Intrinsity Domino logic technology to crank up the speed of its processors to 600MHz.
So I guess the correct comparision would be at block level or if you have a synthesized design on both domino and static logic tech, then you can compare critical paths.
Kr
Avi
http://www.vlsiip.com
 

    gliss

    gliss

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I meant when characterizing a single block or cell.
For a domino logic cell, the propagation delay would be from clock edge to output edge?
And then you compare that to the propagation delay of the static cell which is from input edge to output edge?
 

Yes, the delay in domino logic would be measured from clock-to-output. Still not sure if this delay may be compared one-to-one with a delay of input-to-output of a conventional gate. Because there are also set-up times involved then. So in comparison, not only clock-to-o/p should be taken into account, but also the setup time.
Kr,
Avi
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    gliss

    gliss

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