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You cant really calclate that number. You can probably get some typical times from Xilinx but really the access times are going to depend on how things route from the pins to the BRAM.
That timing info is at the BRAM unit itself. It does not take into account any routing of internal siganls to the BRAM.
That is why it is so important to make sure you specify your timing contraints for signals going to the BRAM. Otherwise if you let the place and route tool decide how to route your signals you could end up with a very long route just to get to or from your BRAM.
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