Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

waveform generate for simulator

Status
Not open for further replies.
W

wwwrabbit

Member level 1
Joined
Jul 17, 2003
Messages
36
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,286
Activity points
344
Xilinx ISE5.1
I want to generate a input signal, which is asychronize to clock. of course I can draw the signal in the test bench. I wonder if I can programe the signal in my .vhl file, so that the signal vary as per my design.

I tried this,
wform <= '0', '1' after 8 ns, '0' after 13 ns, '1' after 50 ns;

but wform won't change.

:?: :?:
 

Please ...... give me a answer. I am waiting.
May I use "delay"
 

Maybe It is synopsys statement.

I think that it can ISE 4.1.

only I think
 

wform <= '0';
wait for 8 ns ;
wform <= '1';
wait for 13 ns ;
wform <= '0';
wait for 50 ns ;
wform <= '1';

... for a testbench... not for synthesis purpose !
 

Delays are not synthesisable. It wont work on the device.
You will have to develop a synchronous circuit to generate those delays.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top