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regarding post PnR timing simulation...

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kil

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hi all,

i have done the post place and route timing simulation for my design. i am getting the following warnings . there is a setup time voilation but can any one explain what this statment means

Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/deframer_inst_fifo_inst_bu236
# ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK;
# Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns
is that my data is arriving early than the expected ... can any one explain me what that warnings means and how can i make sure in my design to avoide this kind of warning .. that does this kind of warning do matter when i am loading my design into silicon. as my logic is not working on the actual silicon.


regards
kil
 

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