crystal
Advanced Member level 4
I have a design, named aaa which consists of ram generated using Core Generator. The ram design generated consists only io ports.
So, i take this design aaa into Xilinx ISE ver 5.1. When i read it at Translate Level, it fails, giving error message saying that it couldn't resolve the module for ram.
How should i read in my files? How does Xilinx ISE5.1 looks for the ram design? It doesn't seemed to be reading it.
Can someone help?
Thanks in advance.
So, i take this design aaa into Xilinx ISE ver 5.1. When i read it at Translate Level, it fails, giving error message saying that it couldn't resolve the module for ram.
How should i read in my files? How does Xilinx ISE5.1 looks for the ram design? It doesn't seemed to be reading it.
Can someone help?
Thanks in advance.