Help me write test codes for shift register

hi all...i am trying on codes for shift register...does anyone can help me to write a test codes so that i can try them out? pls guide too where to input n output the pins on UP2 board using CPLD..thanks!

library ieee;
use ieee.std_logic_1164.all;
entity shift_register4 is
port(reset: in std_logic; clk: in std_logic; si: in std_logic;
s0: out std_logic; q: out std_logic_vector (3 downto 0));
end entity shift_register4;
architecture behavioural of shift_register4 is
signal shift : std_logic_vector (3 downto 0);
begin
process(si,clk,reset)
begin
if (reset = '1')then
shift <= "0000";
elsif (clk'event and (clk = '1')) then
shift <= shift(2 downto 0) & si;
end if;
end process;
q <= shift;
s0 <=shift(3);
end behavioural;


thanks!!!

Re: shift register

I write a simple testbench, and you can write a more comprehensive testbench.

entity tb_shift_register4 is

end entity tb_shift_register4;

architecture behav of tb_shift_register4 is
signal reset: std_logic:='1';
signal clk : std_logic:='0';
signal si : std_logic;
signal s0 : std_logic;
signal q : std_logic_vector(3 downto 0);

signal cnt8 : unsigned(2 downto 0);
signal temp : unsigned(7 downto 0);

CONSTANT ONE_B_FS :time:= 1000000000.0000 fs;
CONSTANT Fclk :real:= 155.62;
CONSTANT Tclk :time:= ONE_B_FS/Fclk;

begin

shift_u: shift_register4(reset=>reset,clk=>clk,si=>si,s0=>s0,q=>q);

reset <= '1' after 10 ns;
clk <= not clk after Tclk/2;

process(reset,clk)
begin
if reset = '1' then
cnt8 <= (others=>'0');
temp <= (others=>'0');
elsif clk'event and clk = '1' then
cnt8 <= cnt8 + 1;
temp <= temp + 1;
end if;
end process;

si <= temp(7) when cnt8 = 7 else
temp(6) when cnt8 = 6 else
temp(5) when cnt8 = 5 else
temp(4) when cnt8 = 4 else
temp(3) when cnt8 = 3 else
temp(2) when cnt8 = 2 else
temp(1) when cnt8 = 1 else
temp(0) when cnt8 = 0 else
'0';

end behav;

shift register

thanks for helping..may i know how do i connect when i wan to download to UP2 board for testing?both the inputs and outputs... may i know wat is cnt8 and temp for?wat is one_b_fs,Fclk and Tclk? can simply explain how the thing works?i found some error during the "signal cnt8:unsigned(2 downto 0)....."

Re: shift register

The above testbench code can only be simulated in Modelsim enviroment.
In real world, for example your U2P board, you have 2 choice. One is use sierial data and clock generator(PCM etc.). Another is generating data and clock by your CLPD itself.

cnt8 : a counter of 8
temp: temproray data
one_b_fs: one billion fs
Fclk: clock's frequency you supposed.
Tclk: this clock'd period

You can fix that syntax error because I haven't simualte it in Modelsim.
I just tell you a simple example. You can perfect it.

Good luck!