asdf44
Advanced Member level 4
So as said, I've got a 10-bit parallel ADC which I want to run at 100mhz and I want to bring the samples properly back into a the FPGAs 100mhz clock domain (clk100). The FPGA sends a 100mhz output clock to the ADC and it sends back 10-bit samples and a return clock. The output clock is clk100 or derived from it.
So I'm synchronizing multi-bit data samples between clock domains that are identical in frequency. There is going to be a new sample every single clock and the data is used in a real-time feedback loop where low latency is desirable.
This isn't rocket science and I'm generally aware of domain crossing techniques but am looking for other opinions on the best choice for this particular application.
Its also theoretically possible to tune the phase (one way or another) of the output clock to guarantee that the return data can be sampled by my main 100mhz clock, although I've initially ruled this out as unwise for a 100mhz bus with only 10ns to work with.
Thoughts?
So I'm synchronizing multi-bit data samples between clock domains that are identical in frequency. There is going to be a new sample every single clock and the data is used in a real-time feedback loop where low latency is desirable.
This isn't rocket science and I'm generally aware of domain crossing techniques but am looking for other opinions on the best choice for this particular application.
Its also theoretically possible to tune the phase (one way or another) of the output clock to guarantee that the return data can be sampled by my main 100mhz clock, although I've initially ruled this out as unwise for a 100mhz bus with only 10ns to work with.
Thoughts?