vickyuet
Member level 2
Dear All,
I am newbie and lastly I was simulating my own testbenches on Modelsim Simulator.Now I do not know the idea
how to simulate my Verilog HDL testbench codes (not VHDL) in Xilinx ISE.I had already generated my waveform using test bench waveform
editor in xilinx but i am interested in writing and simulating my own hdl code and then checking the functionality of my design based
upon my desired inputs.Any one can guide me through steps or reference to some good material.
---------- Post added at 20:43 ---------- Previous post was at 19:22 ----------
I also knew how 2 create test bench using New Source > verilog text fixture but I am confused and want to know how to do it using ISim,especially if i am to use a core from core generator, is there any special steps I had to look for in that case.Thanks a lot.
I am newbie and lastly I was simulating my own testbenches on Modelsim Simulator.Now I do not know the idea
how to simulate my Verilog HDL testbench codes (not VHDL) in Xilinx ISE.I had already generated my waveform using test bench waveform
editor in xilinx but i am interested in writing and simulating my own hdl code and then checking the functionality of my design based
upon my desired inputs.Any one can guide me through steps or reference to some good material.
---------- Post added at 20:43 ---------- Previous post was at 19:22 ----------
I also knew how 2 create test bench using New Source > verilog text fixture but I am confused and want to know how to do it using ISim,especially if i am to use a core from core generator, is there any special steps I had to look for in that case.Thanks a lot.