doost4
Junior Member level 3
Hello everybody
I'm trying to measure the exact execution time for my VHDL design. The problem is, I don't have a digital oscilloscope to see how many clocks spent for generating the final output. I added a counter to my design for counting the clock cycles, so that by multiplying the clock cycles and FPGA period (20 ns in my case) I could measure the execution time.
The counter code is like below:
But the problem is, when I want to read my counter's value in Chipscope, it shows a irrelevant value. I think there is a problem related to internal clock signals, because the other output registers of design show the correct values in Chipscope.
Do you have any ideas about my problem? Or another way to measure the execution time on FPGA?
My device is Spartan6 lx9 series and I use Xilinx ISE DS 14.7.
Thanks
I'm trying to measure the exact execution time for my VHDL design. The problem is, I don't have a digital oscilloscope to see how many clocks spent for generating the final output. I added a counter to my design for counting the clock cycles, so that by multiplying the clock cycles and FPGA period (20 ns in my case) I could measure the execution time.
The counter code is like below:
Code:
process (clk)
begin
if(rising_edge(clk)) then
counter_b <= counter_b + 1 ;
end if;
end process;
--
process(clk)
begin
if(rising_edge(clk)) then
count_out <= counter_b ;
end if ;
end process ;
But the problem is, when I want to read my counter's value in Chipscope, it shows a irrelevant value. I think there is a problem related to internal clock signals, because the other output registers of design show the correct values in Chipscope.
Do you have any ideas about my problem? Or another way to measure the execution time on FPGA?
My device is Spartan6 lx9 series and I use Xilinx ISE DS 14.7.
Thanks