[SOLVED] Programmable Priority Encoder

Can someone help me in designing a programmable priority encoder using verilog . A programmable priority encoder is a device where in addition to the the normal i/p and o/p's of a simple priority encoder there is one more input to decide which bit should have highest priority. Eg. for 4 : 2 programmable priority encoder..there would be 2 select input to decide the priority say [1:0]S.
If S=00; I0 has highest priority..and the priority order will be I0>I3>I2>I1
If S=01; I1 has highest priority..and the priority order will be I1>I0>I3>I2
If S=10; I2 has highest priority..and the priority order will be I2>I1>I0>I3
If S=11; I3 has highest priority..and the priority order will be I3>I2>I1>I0
..The solution is desired to be generic like the logic should remain same for 8:3 and 16:4 priority encoders as well...
Any suggestions would be very helpful...Please help ASAP!!

So what have you done so far, and what are you having problems with?

Well..my first approach was that to make a 8:3 programmable priority encoder I made eight regular priority encoders and one 8:1 mux . Each priority encoder has a fixed request order, and the multiplexer passes the desired code to the output. But its is not very efficient . I want a logic which is more efficient but nothing is striking my head.

Yeah but I wish to design such a logic in which when a 4:2 programmable priority encoder is converted to a 8:3 programmable priority encoder no major changes have to be made. If you seem to have any idea on how to do it please help me out.

But its is not very efficient.

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I doubt that it matters. You write a behavioral description of the logic function and the synthesis tool tries to minimize the logic.

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I don't see a problem to write a parameterizable generic encoder description which works for N outputs and select inputs respectively 2^N request inputs.

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Btw, the encoder should also have a specific output to "no request set", so you either need to reduce the number of request inputs to 2^N - 1, or use an additional encoder output.

Are you really not getting what I wanna say..See I got a thing here...If we add a left rotator followed by a priority arbiter and then a right rotator followed by an encoder...This would act like a priority encoder..

Its not clear what you really want help with, or what the problem really is.
Have you written any code? have you compared different implementations?

A for-loop version probably works fine.

if not, you can convert it into a rotate + priority encoder + adder, at least for the 2^N inputs case.

There are a few other implementations possible. For example, you can create constants for 10101010, 11001100, 11110000 etc... based on elaboration time constants. Then you can use the "(-x) and (x)" trick to get a one-hot value. each bit of the encoder is then the or-reduction of "constant and one_hot". That sounds interesting, but I'm not sure if it is actually better. The use of the addition should force the tools to use a different implementation method though.

But I'd start by comparing the for-loop version to a more verbose fixed sized version. It doesn't take much time and allows you to determine if the for-loop approach happens to map better to a LUT based implementation.

Please elaborate the one hot method ...Are you talking about masking the input requests or something else..please elaborate it..

The expression "(-x) and (x)" will result in either 0 (if the input is 0), or a vector in which the rightmost '1' is the only bit set. This is easy to show by doing each step of the computation.

If the input has only a single 1, the priority encoder logic is much simpler and can be implemented by doing and-or logic with "10101010", "11001100", and "11110000" (for 8 inputs). This is the vector where the value is '1' for index 0, 1, and 2 respectively.

This method is of interest only as the coding style is different, and it implements the inductive logic using a carry chain.

Can you describe an hardware based design for a programmable priority encoder ..like through rotators encoders etc...

[merged] Programmable Priority Encoder

Help regarding structural modelling of a programmable priority encoder(ppe)...Where different blocks can be coded in behavioral model but overall ppe must be modeled in structural manner...

vGoodtimes said:

A for-loop version probably works fine.

if not, you can convert it into a rotate + priority encoder + adder, at least for the 2^N inputs case.

There are a few other implementations possible. For example, you can create constants for 10101010, 11001100, 11110000 etc... based on elaboration time constants. Then you can use the "(-x) and (x)" trick to get a one-hot value. each bit of the encoder is then the or-reduction of "constant and one_hot". That sounds interesting, but I'm not sure if it is actually better. The use of the addition should force the tools to use a different implementation method though.

But I'd start by comparing the for-loop version to a more verbose fixed sized version. It doesn't take much time and allows you to determine if the for-loop approach happens to map better to a LUT based implementation.

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Can you please elaborate the rotate + priority encoder+ adder method...Please explain it ...How it works?

It is just as it sounds. post #10 shows how to construct a priority encoder using an adder to generate a 1-hot logic signal, and then a set of bitmasks to generate each output bit. to change the priority order would be a barrel shifter (rotate).

Depending on width and clock rate, the combined operation may require multiple cycles.

Which post 10? ..Can you please explain it again step by step...I didn't get you! How to form a Ppe using rotator priority encoder and an adder...Thanks...

At this point, you should post your current progress or give-up. Multiple solutions to your problem have been posted over the last three months. At this point it isn't clear if you just want others to do everything for you or if this problem isn't important to you.

I have made one working ppe already using masking technique..But I have to submit another ppe with different logic ..The problem is I can't use behavioral modelling..That is I can't code in behavioral style..I need to do it in structural modelling(not using only gates) but rather using components leq . mus or adder etc . Like you mentioned few answers have been posted for my query but most of them use behavioral style..like using for loop etc..So as i said I have made one using masking and muxes ..but the logic for a second ppe isn't striking..I just need the logic like you once said that I can use rotator + priority encoder+ adder...But what would be the inputs to adder..Just please explain the logic a bit....

As mentioned, the priority encoder is created from the logic: (x) & (-x), followed by |(x & mask). The goal is to get a vector that retains only a single one and has it in the rightmost location.
for example x = 11001000, (11001000) & (00111000) = (00001000)
from there the masks can be used:
sel[0] = |(00001000 & 10101010) = 1,
sel[1] = |(00001000 & 11001100) = 1,
sel[2] = |(00001000 & 11110000) = 0.
thus sel = 3, which is the index of the lowest 1 in the original input of 11001000.
This method is only interesting because it makes use of the adder, which means there is an implementation difference in an FPGA. Unless the synthesis tools can detect the and-xor logic in a different implementation.

The other way I can think of to make a generic priority encoder would be to define:
tmp[2] = (x & 11110000); sel[2] = |tmp[2]
tmp[1] = (tmp[2] & 11001100); sel[1] = |tmp[1]
tmp[0] = (tmp[1] & 10101010); sel[0] = |tmp[0]
This leans on the synthesis tool to optimize the logic though. I'm fairly sure this generates extra gates compared to something that isn't generic. But generate statements make this easy enough to write in a structural manner. I guess just enable global optimizations to make up for a pointless constraint.

But overall this sounds like a really bad project. Unless there is some trick, this doesn't look like a problem that is well solved by structural modeling. This seems like something that forces the student to write code poorly which doesn't really serve to teach the student nor prepare them for a career. The only point this serves is that just because you can do something doesn't mean you should. Really, the structural techniques taught in classes are often very misapplied.

ah, ok. I see what the project was.

I think this project was to show this masking idea. I hadn't seen it before but it makes sense.

There are four ppe's that could be compared. There is the one from the book -- that has two mask and two priority encoders and a mux on the output. There is also a version that has N priority encoders and an output mux. There is also this barrel shifter version that allows a single encoder. There is also a version that does the masks and then determines which mask would be best and then has a mux on the input. Because the book mentions two options -- the one that is depicted with a diagram and a version that has N priority encoders and a mux -- I suggest you focus on these two. This will let you post the results and conclusions reached in the book.

vGoodtimes said:

But overall this sounds like a really bad project. Unless there is some trick, this doesn't look like a problem that is well solved by structural modeling. This seems like something that forces the student to write code poorly which doesn't really serve to teach the student nor prepare them for a career. The only point this serves is that just because you can do something doesn't mean you should. Really, the structural techniques taught in classes are often very misapplied.

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"Structural modelling" is a technique used by unis (and some old time engineers) because students will first learn the schematic representations of all the gates, and it is a logical first step at transfering from paper based schematics into HDL. The only problem is the capability of most teachers isnt much more than this either, so student come away thinking this is an acceptable style in the real world.