msdarvishi
Full Member level 4
Dear all,
I am using Vivado 2017.1 targeting a Zynq-7000 clg484 Xilinx FPGA.
I have implemented a ring oscillator and a period counter circuit both implemented on the FPGA. My objective as a course project is to measure the frequency of ring oscillator using the period counter circuit. To do so, I connected the output of ring oscillator to the clock input of period counter directly without any buffer or something else, it is just a simple routing wire. Primarily in SYNTHESIS navigation menu in Vivado, I did right-click and set -bug to 0 avoid using clock trees in my design. (Default value for bufg was 12). After implementation, I saw that the registers of my period counter did not receive clock signal and I see the "No clock" critical warning as seen in the attached figures along with a closed view of registers without clock.
As the first guess, I thought maybe this is due to the bufg value that I already set to 0 in SYNTHESIS menu, so I changed it to its default value (12) and re-implemented my design. But still the problem exists and my period counter does NOT count anything !!!
Here is the message received by Vviado. The "xn_inferred_i_1" is the output of ring oscillator that is connected to the CLK pin of period counter module.
Can anyone help me to solve this problem, please? I am in rush to finish this work and this crazy issue has stopped me !
Kind replies and helps are in advance appreciated.
Regards,
I am using Vivado 2017.1 targeting a Zynq-7000 clg484 Xilinx FPGA.
I have implemented a ring oscillator and a period counter circuit both implemented on the FPGA. My objective as a course project is to measure the frequency of ring oscillator using the period counter circuit. To do so, I connected the output of ring oscillator to the clock input of period counter directly without any buffer or something else, it is just a simple routing wire. Primarily in SYNTHESIS navigation menu in Vivado, I did right-click and set -bug to 0 avoid using clock trees in my design. (Default value for bufg was 12). After implementation, I saw that the registers of my period counter did not receive clock signal and I see the "No clock" critical warning as seen in the attached figures along with a closed view of registers without clock.
As the first guess, I thought maybe this is due to the bufg value that I already set to 0 in SYNTHESIS menu, so I changed it to its default value (12) and re-implemented my design. But still the problem exists and my period counter does NOT count anything !!!
Here is the message received by Vviado. The "xn_inferred_i_1" is the output of ring oscillator that is connected to the CLK pin of period counter module.
[Place 30-568] A LUT 'xn_inferred_i_1' is driving clock pin of 51 registers. This could lead to large hold time violations. First few involved registers are:
prd_contr/delay_reg_reg {FDCE}
prd_contr/p_reg_reg[0] {FDCE}
prd_contr/p_reg_reg[10] {FDCE}
prd_contr/p_reg_reg[11] {FDCE}
prd_contr/p_reg_reg[12] {FDCE}
Can anyone help me to solve this problem, please? I am in rush to finish this work and this crazy issue has stopped me !
Kind replies and helps are in advance appreciated.
Regards,