msdarvishi
Full Member level 4
Dear all,
I am designing some ring oscillators implemented in a Zynq 7000 FPGA and I have designed a period counter in order to measure the frequency of each ring oscillator. The clock signal of period counter is the output signal of the ring oscillator. My period counter is a synchronous counter that means all of its D flip-flops change state at the rising edge of the clock signal.
My teacher said you HAVE TO come up with an Asynchronous period counter than a synchronous one since the number of clock trees in FPGA is limited and if you put for example 100 ring oscillators each individually connected to a period counter, you will see the problem of lack of the number of clock trees. First of all, is it correct??
He also says, you have to force Vivado (I use 2017.1 version) NOT TO USE clock trees in your design and you have to change your period counter to an asynchronous one designed with T flip-flops. Is it possible to avoid using clock trees in design by a command or constraint in Vivado? Can you please let me know how?
Also, my current period meter works very nice but I have no idea how to change it to an asynchronous by T flip-flops??!! Can anybody help me with those issues, please?
kind replies and help are in advance appreciated.
Regards,
I am designing some ring oscillators implemented in a Zynq 7000 FPGA and I have designed a period counter in order to measure the frequency of each ring oscillator. The clock signal of period counter is the output signal of the ring oscillator. My period counter is a synchronous counter that means all of its D flip-flops change state at the rising edge of the clock signal.
My teacher said you HAVE TO come up with an Asynchronous period counter than a synchronous one since the number of clock trees in FPGA is limited and if you put for example 100 ring oscillators each individually connected to a period counter, you will see the problem of lack of the number of clock trees. First of all, is it correct??
He also says, you have to force Vivado (I use 2017.1 version) NOT TO USE clock trees in your design and you have to change your period counter to an asynchronous one designed with T flip-flops. Is it possible to avoid using clock trees in design by a command or constraint in Vivado? Can you please let me know how?
Also, my current period meter works very nice but I have no idea how to change it to an asynchronous by T flip-flops??!! Can anybody help me with those issues, please?
kind replies and help are in advance appreciated.
Regards,