birbal
Newbie level 5
I'm using a Digilent Nexys4 development board with Vivado v2017.1 and verilog for the code. My design uses a master clock (clk) of 100MHz. In of my modules I generate a 2 MHz clock (sclk) as follow:
Where in this case TICKS_SCLK is set to 50 to generate a 2 MHz clock. Then I use the sclk in the same module to have an FSM process as:
Inside of this FSM are only non-blocking assignments (<=). In simulation everything works fine. After implementation, when I upload the desing into the board, the circuit behaves differently. I hooked up a logic analyzer to understand what is happening. The sclk is indeed 2 MHz with 50% duty cycle as intended. However everything what is inside of that process with negedge sclk seems to happen at any edge of sclk (posedge or negedge). I can't figure it out where is the problem.
- - - Updated - - -
After a bit more research I found out that I need to put a user defined generated clock constraint. Something like: create_generated_clock -name sclk [get_nets MCP3208/sclk_OBUF] . However at the moment I have issues in getting the net quite right. Not sure why this is giving me an error. I can see in the shcematic after synthesis that MCP3208/sclk_OBUF is the name of the net of generated clock.
Code:
always @ (posedge clk) begin
if (adc_en) begin
if (clock_count < TICKS_SCLK -1)
clock_count <= clock_count + 1;
else
clock_count <= 16'b0;
end
end
assign sclk = clock_count > ((TICKS_SCLK-1)/2);
Code:
always @ (negedge sclk) begin
...
...
end
- - - Updated - - -
After a bit more research I found out that I need to put a user defined generated clock constraint. Something like: create_generated_clock -name sclk [get_nets MCP3208/sclk_OBUF] . However at the moment I have issues in getting the net quite right. Not sure why this is giving me an error. I can see in the shcematic after synthesis that MCP3208/sclk_OBUF is the name of the net of generated clock.