roshan12
Junior Member level 2
It is not possible to create a system design comprising of two MicroBlaze processors operating at the same time. I used the base system builder wizard in Xilinx EDK 10.1 to design the system. Initially I built a single processor system and then tried to add the second processor IP (from IP catalog). But when creating the netlist for the system the following error occured:
The issue I suppose was with clock signal not connected to the processor IP. I didn't find any options to connect the same. What might I be doing wrong??
P.S: the processors are not intended to be used as multi-cores. They should be individually operating embedded processors
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
ERROR:MDT - issued from TCL procedure
"::hw_microblaze_v7_10_a::check_iplevel_settings" line 6
microblaze_1 (microblaze) - The CLK signal is not connected. MicroBlaze
cannot work without a correct CLK signal input.
ERROR:MDT - platgen failed with errors!
Done!
The issue I suppose was with clock signal not connected to the processor IP. I didn't find any options to connect the same. What might I be doing wrong??
P.S: the processors are not intended to be used as multi-cores. They should be individually operating embedded processors