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  1. Replies
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    Closed: Re: Better performance measure LUT vs FF

    Thanks guys!

    I guess by better I meant in terms of resource. I know both designs work and well written. Given all information, would I choose the design with less FF or LUT was my question....
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    Closed: Re: Better performance measure LUT vs FF

    Thanks TrickyDicky.

    A and B are completely different designs trying to achieve the same thing. I do understand that the clock, DSP, BRAM etc are important constraints/meterics.

    Maybe...
  3. Replies
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    Closed: Better resource utilization measure LUT vs FF

    Hello,

    A basic question here. If two designs A and B get synthesized and result in a utilization report of:

    A: x LUTs and y FFs
    B: x/2 LUTs and 2y FFs

    Which one would be a better design...
  4. Closed: Run all Vivado synthesis strategies in one run

    Hello,

    Is there any way that I can synthesis my design using all the 8 synthesis strategies(optimized area, performance...) available in Vivado and have one synthesis report for each? Now the...
  5. Replies
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    Closed: Re: Efficient SerDes-Like Module

    I like your method.:clap: But in my case switching to that kind of memory configuration will add unnecessary addressing complexity and additional modules. Thanks!
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    Closed: Re: Efficient SerDes-Like Module

    Your approach is ideal if you have fewer number of samples. In my case, the RAM is 62500x16bits containing image pixels and I have a minimum of 64 PEs. If I changed the dimension to what you...
  7. Replies
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    Closed: Efficient SerDes-Like Module

    Hi folks,

    In my design I have N(could range from 64 to 1024) number of processing elements, each PE taking x samples at a time. I would like to feed all N PEs and trigger their processing at the...
  8. Closed: [moved] Formal verification, Model Checking

    Hello,

    I would like to know the best book for Formal Verification for a complete newbie? Any useful links are also appreciated.

    Best,
  9. Closed: CLOCK_50 was determined to be clock but was found without an associated clock assign.

    Hello,

    I am having an issue in combining two clocks signals in one project. I am using DE2 Altera board. I am also using Nios processor. So, basically I am trying to merge to independently...
  10. Closed: Re: Locating a robot in an indoor and noisy environment

    I would like to assume the worst possible environment so I can consider all the possible challenges and make a generic solution. For example an indoor environment with lots of partitions and lets...
  11. Closed: Locating a robot in an indoor and noisy environment

    Hi y'all,

    I was looking for the best and accurate way of locating a moving robot in an indoor environment. I have seen some technologies using WI-FI, RFID and bluetooth to measure the signal...
  12. Closed: Re: XY mode Oscilloscope plot scale reading

    Hi Chucky, thank you for your reply. This is not for calibrating a CRO. This is to see a sampled signal given a sinusoidal wave form. So, I gave the sample and hold circuit output for X and a...
  13. Closed: Scale reading XY plot Oscilloscope

    Hello,

    I have a sawtooth signal driving the X(period of Ts, k ms/div, m V/div and slope of A volts/sec) and Y driven by a sin wave (1 Hz, 1Vpp, B volts/div, p ms/div). It is clear that I will...
  14. Closed: XY mode Oscilloscope plot scale reading

    Hi,

    I was wondering how we can read an XY plot regarding scaling.

    For instance if I drive X by a sawtooth (period of Ts and slope of A volts/sec) and Y by a sin wave of(1 Hz, 1Vpp, B...
  15. Closed: Re: Timing issues in Xilinx and SmartXplorer

    Yes it is 16K FFT report. The thing is I had very large shift registers build from LUTs which made my synthesis very very slow, to be exact 8+ hours. Then I noticed that and changed it to RAM bases...
  16. Closed: Re: Timing issues in Xilinx and SmartXplorer

    Hey, thanks for the reply. Full version 14.7. Find the attached text please.
    And how can I partition my design btw, have never done that.
  17. Closed: Timing issues in Xilinx and SmartXplorer

    Hi,

    My design has the following timing issues.

    Period Required: Actual period:
    4.096ns 6.058ns
    8.138ns ...
  18. Replies
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    Closed: Re: ISE run out of Memory

    All the solutions are costly. :) Thank you for the reply, I will see which one I will choose.
  19. Replies
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    Closed: ISE run out of Memory

    Hi,

    ISE 14.7, Win 7, 4GB(3.5 usable)
    I have the following message when I try to simulate a project from command line. Surely, the project needs quite a lot of memory but I am worried that...
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    Closed: Re: ISim terminated in unexpected manner

    Finally you nailed it!!!:):thumbsup: After you remind me, I cleaned up the project files and rerun again, works superb! Thanks a lot man! :wink:
  21. Replies
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    Closed: Re: ISim terminated in unexpected manner

    I mean there is still enough space(40%) not to run out of memory. :)

    Tried running from command line, the same message appeared and testbench_isim_beh.exe is 81KB.


    A bit less memory...
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    Closed: Re: ISim terminated in unexpected manner

    Hey, I tried to watch task manager, I see a strange thing. Right on the start the Memory the ISim takes increases to around 500MB and then wefault.exe(Windows problem reporting) started and just then...
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    Closed: ISim terminated in unexpected manner

    Hi,

    I have a generic design for processing FFT, where I decide the number of points in the beginning. The design is working ok, for anything less than 4096 points, but when I put the number of...
  24. Closed: Re: Inferring DSP48s(four slices) as 35x35 muliplier

    Now it is working, thank you though.
  25. Closed: Re: Inferring DSP48s(four slices) as 35x35 muliplier

    Great! I also changed the numbers to signed, the synthesis works fine. While implementing I have this message, I am unable to see how it is implemented. Have you came across this massage by any...
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