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Type: Posts; User: rafimiet

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  1. Replies
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    168

    Closed: Re: Timing simulations in vivado

    Is there any relation between worst pulse width slack and clock period? I mean is period = 2*WPWS? Also I want your recommendations about the approach to fix the error for minimum possible clock...
  2. Replies
    4
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    168

    Closed: Timing simulations in vivado

    I get the following timing report after implementing design for 10ns clock period
    141227
    Does it simply mean that I have to increase the clock period? Or it means I have to make some input/output...
  3. [SOLVED]Closed: Re: "ERROR: [Common 17-165] Too many positional options when parsing

    Both the errors have been rectified by
    1) Avoiding spaces in the absolute path of the project as rightly said by ads-ee

    2) By providing the absolute path of the text file. In ISE, I was placing...
  4. [SOLVED]Closed: Re: "ERROR: [Common 17-165] Too many positional options when parsing

    Can you please elaborate on this wrt above code?
  5. Closed: Re: Initializing a very long vector with some repetition

    I have a very long code using Finite State Machine. Here I attach the code. The code is sequential, so using signal provides output only on the next clock cycle. Also I sometimes need to update the...
  6. [SOLVED]Closed: "ERROR: [Common 17-165] Too many positional options when parsing

    I try to simulate a design with the test bench as follows:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE std.textio.all;

    -- Uncomment the following library declaration if using
    -- arithmetic...
  7. Closed: Re: Initializing a very long vector with some repetition

    The vhdl code is as follows:

    GENERIC(LLrow: INTEGER := 16);
    SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ;
    variable row : INTEGER RANGE 1 TO N := 1;
    variable addr2_2 :...
  8. Closed: Initializing a very long vector with some repetition

    I have to initialize a very long vector in the pattern such as

    What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.
  9. [SOLVED]Closed: Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL

    I needed to use both sla and sra. Then I can use the function you provided above for sra and sll for sla.
  10. [SOLVED]Closed: Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL

    I am actually working on Xilinx ISE 14.2.

    when I try this,

    which is a positive number!!
  11. [SOLVED]Closed: Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL

    I have selected VHDL-200X and the code is as follows:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity shift is
    Port ( din : in STD_LOGIC_VECTOR(7 downto 0);...
  12. [SOLVED]Closed: shift left(or right) with arithmetic operation for data type SIGNED in VHDL

    I have to use shift operation for signed data type. sll and srl are synthesizable, however sla and sra are not. How can I perform them?
  13. Replies
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    176

    [SOLVED]Closed: ERROR:HDLParsers:3375

    I have a vhdl code, which has a line as below:

    variable thrsh : STD_LOGIC_VECTOR(7 downto 0);
    SIGNAL n : INTEGER RANGE 0 TO 7 := 7;
    thrsh := (n => '1', OTHERS => '0');
    'n' initially is the...
  14. Closed: Re: simulation in vivado vs ISIM(in Xilinx ISE)

    But ISIM is not there. Is there a way to enter manual simulations?
  15. [SOLVED]Closed: Re: how to locate the addresses of 1's in std_logic_vector

    The source is a still/video camera. It will add up to my work if we can process more than 30 frames a second.

    After acquiring the image, I have to apply 5 levels of Discrete wavelet transform,...
  16. [SOLVED]Closed: Re: how to locate the addresses of 1's in std_logic_vector

    I have a vector A(256*256-1 downto 0) that gives me the address to a block of pixels in an image. Starting from LSB to the MSB, when I encounter a '1' bit, I have to move to the next state in the...
  17. [SOLVED]Closed: Difference between combinational path delay and minimum period

    After synthesizing, I get the static timing report as follows


    Minimum period: 7.577ns (Maximum Frequency: 131.987MHz)
    Minimum input arrival time before clock: 2.325ns
    Maximum output...
  18. Closed: Re: merging two coloumns of a matrix into one vector using matlab

    In simple you can use this command dec2bin(x,n). For example

    dec2bin(7,3)
  19. Closed: simulation in vivado vs ISIM(in Xilinx ISE)

    I have been using Xilinx ISE and ISIM for quite a few years now. But now, due to some reasons, I have to switch to Vivado. I can not find the simulation setup in vivado the same way as ISIM. Also I...
  20. [SOLVED]Closed: Re: how to locate the addresses of 1's in std_logic_vector

    I tried to implement a small code as per your recommendations


    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create...
  21. [SOLVED]Closed: how to locate the addresses of 1's in std_logic_vector

    I have a std_logic_vector signal, namely A of 2048 bits, 2047 downto 0, I want to locate the positions (addresses) of '1' bits in the vector. These addresses need to be stored into an array B in...
  22. [SOLVED]Closed: Re: Parameters like speed, area and power after dumping on FPGA board

    The voltage supplied to the board remains the same, so we have to find the current that goes into the board and multiply the two. Is that how to find out power?

    I mean the total time to process a...
  23. Closed: Re: 3 LCD Screen support via HDMI and Direct connect with an FPGA

    Read about FPGA Extension boards. Here are some links to read and analyze them

    https://www.xilinx.com/products/boards-and-kits/fmc-cards.html...
  24. [SOLVED]Closed: Re: Parameters like speed, area and power after dumping on FPGA board

    So, you mean area need not be checked after dumping the design. Can I somehow extract the parameters from the board?
  25. Closed: Re: 3 LCD Screen support via HDMI and Direct connect with an FPGA

    There is no such board which can give you such versatility, however, you can buy some FMC boards along with FPGA boards which support multiple HDMI IN/OUT ports.
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