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soc encounter question
hi friends,can someone tell me whether cadence soc encounter can be used tobuild socs with fpga hard macros (ip)? if not what tool can do that?thanks in advance...
ASIC Design Methodologies & Tools (Digital) :: 09 Sep 2009 3:05 :: kolla :: Replies: 8 :: Views: 492
how clk timming affects a design in fpga?
hi friends!, im doing a qpsk communication project.and using virtex-4,xilinx ise8.2i. my adcs and dacs require 100 mhz as clk input in order to work. in our circuit,we have not provided a separate cr...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Jul 2009 7:01 :: xtcx :: Replies: 0 :: Views: 117
digital oscilloscope project
hii m studying possibilities to make a digital oscilloscope for pc, with onboard ram to memorize samples.i have several questions : => wich bus is the easier to use (hard and driver for linux/windows)...
Hobby Circuits and Small Projects Problems :: 03 Jul 2009 12:05 :: millwood :: Replies: 474 :: Views: 270061
icd3 clone
hi everybody,the new debugger of microchip, icd3, is released.. with a price of 220$ vs 160$ for icd2 !for the previous version, we saw very well works to make it more accessible for the elctronic ama...
Microcontrollers :: 25 Jun 2009 21:00 :: blueroomelectronics :: Replies: 16 :: Views: 8103
orcad and pld
i run programmable logic project wizard in orcad, there is no atmel vendor. only actel, altera and xilinx.thanks in advance.pavel....
PLD, SPLD, GAL, CPLD, FPGA Design :: 25 Mar 2009 4:21 :: Mr.Cool :: Replies: 2 :: Views: 573
suggestions for an fpga development board purchase.
an learn the basic of the fpga desiging what will be good cyclone ii fpga starter development kitor xilinx spartan-3e fpgai will be gladfull if i get information on some other good kits , thanks...
PLD, SPLD, GAL, CPLD, FPGA Design :: 31 Jan 2009 12:44 :: kvingle :: Replies: 11 :: Views: 1659
pcb/schematic/fpga/processorsprogramming/electronics designs
patible;• in accordance with the rules of design for test;– designing hdl modules to fpga systems:• xilinx, altera, actel, cypress;– designing systems on chip:• microblaze, picoblaze, niosii, others;–...
Business Special Interest Group :: 15 Sep 2008 10:33 :: Zbigniew N :: Replies: 0 :: Views: 396
fpga to pcb
hi!im new to here!i took a course in vhdl, but im having a trouble by doing a real project.basically i ordered the cyclone ii tqfp 144 pin, but then it says bake the chip. the moisture sensitivity str...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Aug 2008 9:28 :: FvM :: Replies: 4 :: Views: 228
regarding fpga board design
dear all,i am new to fpga board design, may i know the basic steps to be followed in the fpga design board and may i get any reference books for this.thanks,r balasubramaniaraju...
PCB Routing & Schematic Layout software & Simulation :: 04 Apr 2008 22:17 :: echo47 :: Replies: 1 :: Views: 195
[req] - experience with fpga with built in serdes
8o on pcb or/and cablealtera or xilinxtia :d...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02 Apr 2008 9:14 :: grigodedes :: Replies: 9 :: Views: 1052
what is a serdes?
can someone here clarify what is a serdes?what applications/designs it is being used?what are the design guidelines to be considered when doing design/layout of serdes circuits?...
Professional Hardware and Electronics Design :: 27 Feb 2008 13:12 :: JABEZ.S.DAVID :: Replies: 2 :: Views: 306
problem with xc18v04 and xc3s400
400 and xc18v04 as fpga and prom. for performing the project i made a pcb based on the circuit from xilinx application note xapp453 the 3.3v configuration of spartan-3 fpgas as below:http://images.ele...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Feb 2008 5:34 :: tkbits :: Replies: 1 :: Views: 141
being an electrical engineer
hello everyone ！！i am a student in elecrical engineering i want to know being an electrical engineer ,what is the enssiential software that i must to lerarn------hope someone can help me...
Professional Hardware and Electronics Design :: 13 Feb 2008 11:14 :: gigahertz :: Replies: 16 :: Views: 1890
want to design a pcb with an fpga on it?
t to design a pcb with an fpga on it, but it seems i can not find official documents from altera or xilinx on how the pins should be connected. on most circuits ive used (simple ics in comparison) the...
Hobby Circuits and Small Projects Problems :: 05 Feb 2008 21:28 :: FvM :: Replies: 4 :: Views: 186
ise vs qu(at)rtus
im a quartus user. recently, i have to use xilinx tool to synthesize and simulate. but, im really confused because theres a lot of thing i didnt know about xilinx tools....
PLD, SPLD, GAL, CPLD, FPGA Design :: 01 Feb 2008 19:12 :: Iouri :: Replies: 4 :: Views: 174
fpga hardware (pcb) design
hi, i will be required to start working on desinging custom fpga board (for some algorithm evaluation ) including a device from virtex family...i am new in this era kindly help me in any way u cani w...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Jan 2008 15:23 :: Koson :: Replies: 3 :: Views: 295
high-speed pcb decoupling caps selection?
hi,im doing a board with a cyclone ii and i will need to choose decoupling capacitors for it. im planning to use fr4 with a power and gnd plane. after a fair bit of study it seems like i should use 0....
PCB Routing & Schematic Layout software & Simulation :: 17 Dec 2007 10:25 :: buenos :: Replies: 9 :: Views: 519
free lancers
.we are specialized in:1. embedded system development. (arm based, pic based, rabbit/zilog based)2. xilinx based fpga development. (we did virtex 5, 4, spartan 3)3. pcb layout (6 to 8 layer, high spee...
EDA Jobs, Promotions, Advertising :: 07 Dec 2007 13:28 :: Impressa :: Replies: 2 :: Views: 312
first xilinx fpga board design,what to choose?
i would like to design first fpga board soon,for experimenting with vhdl doing custom microprocessors.. which device do you advice me to select? virtex5,4? spartan? which chip? i am also planning to p...
PLD, SPLD, GAL, CPLD, FPGA Design :: 20 Oct 2007 0:52 :: echo47 :: Replies: 4 :: Views: 402
want to make a fpga board
i am not familiar with the electric engineering. but i am interested in the fpga. can anybody tell me how to make a fpga board? tools to design the pcb? any knowledge to design the power? thanks a l...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Oct 2007 17:35 :: Iouri :: Replies: 15 :: Views: 909
input and output delay budgeting for 2 fpga
ftually we specified the expected input delay for fpga 2? does this information can ge get from the xilinx par report? or trace report?any document regarding to this issue?thank you very much...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Jul 2007 19:47 :: echo47 :: Replies: 1 :: Views: 153
download cable iii with spartan-3
as you know xilinx download cable iii circuit works with 5v and spartan-3 is 3.3v tolerant. i have a question which may seems funny.is it possible to connect download cable iii(which works with 5v) di...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 May 2007 10:19 :: yego :: Replies: 2 :: Views: 495
weird problem. help needed
gangs,i am working on ddr memory controller targeting xc4vfx60-10 with mt46v32m16p-5b. the tools is xilinx mig17.first, i designed a memory controller (16bits) for one mt46v32m16p-5b chip only. it is ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 May 2007 18:53 :: banjo :: Replies: 5 :: Views: 561
freeware spice or ibis simulator for xilinx models?
does anyone know of any freeware simulators that work with xilinx spice or ibis models? i tried the linear tech simulator and another engineer in the office tried to use the texas instrument simulato...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 May 2007 3:26 :: banjo :: Replies: 0 :: Views: 453
fpga routing
tellme about a tutorial on routing and plcement in xilinx ise8.2i...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Apr 2007 9:38 :: vinodkumar :: Replies: 4 :: Views: 651
uart (1v8 and 2v8) interface to xilinx spartan3 - help need
hello, i have one module that has two operating uart, uart1 is 2v8, and 3v tolerant. uart2 is 1v8. i want to interface these uart to a spartan3 fpga, which i believe i/o signals are [0..+3.3v]. do i...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Mar 2007 18:48 :: banjo :: Replies: 4 :: Views: 243
same features & pin compatiblity with xilinx cpld
hi,now i am using xilinxs cpld xc9536xl-44pin.i want cpld from another manafacturer having same features & pin compatiblity with xc9536xl.for this should i do any other changes with my pcb also so th...
PLD, SPLD, GAL, CPLD, FPGA Design :: 22 Mar 2007 13:15 :: prajit :: Replies: 2 :: Views: 129
company in eu offering services
are offering sw/fpga/pcb solutions at competitive prices. our expertise is number crunching in fpga(xilinx, lattice, altera) backed by academic research (signal processing, numerical algorithms), prot...
EDA Jobs, Promotions, Advertising :: 08 Feb 2007 14:45 :: Mazi3 :: Replies: 0 :: Views: 183
lookup table with cpld or fpga?
2bits). i prefer to use cpld because it do not need any prom in pcb. can you suggest me a cpld from xilinx (for example xc9500) that can implement this lookup table and two (16 bits) dividers and two ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 28 Jan 2007 6:47 :: my_garden :: Replies: 2 :: Views: 153
need urgent help for xilinx fpga!!!
by accident, we have connected the vcco for lvds output signals from 2.5v to 3.3v on pcb.we still can assign the signals to lvds level inside program, but the i/o voltage at outside is 3.3v.what we s...
PLD, SPLD, GAL, CPLD, FPGA Design :: 19 Sep 2006 18:26 :: Gunship :: Replies: 1 :: Views: 231
who to chose fusion fpga or cyclone ii fpga?
lerning experiments and found ofcours alteras cyclone ii series (i am intrested in ep2c8q208c8) and xilinx spartan 3 and lattice and new actel fusion series m7afs600. so which is the best one to start...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Sep 2006 8:57 :: Epis :: Replies: 7 :: Views: 1293
xilinx ise coregenerator...is it really usefull?
i am not sure about ise coregenerator.... can we say that this is like other compiler that are not as optimised as manual coding?!!my question is : is the final result of these automatic coregenerator...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02 Jun 2006 6:22 :: JaneZhong :: Replies: 5 :: Views: 504
xilinx fpga router error,can someone heip me?
hello everyone, i use a pair of lvds signals as the differential clks of dcm,when implementing the design ,i encounter an error as follow:this design contains an lvds pair.the pair of ios must be palc...
PLD, SPLD, GAL, CPLD, FPGA Design :: 30 May 2006 5:25 :: shoufeng_luo :: Replies: 3 :: Views: 141
how to design a soc?
i want to study to design a soc , and where to find a soc design example?open_cores?...
ASIC Design Methodologies & Tools (Digital) :: 14 Apr 2006 13:22 :: SkyHigh :: Replies: 12 :: Views: 720
can i build an fpga kit? need your suggestions plz
hello,you may know that theres a varity of microcontrollers programmers, kits, and manyother test boards and whatever for many types of microcontrollers that can be built, however therere many other k...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Apr 2006 23:38 :: gliss :: Replies: 6 :: Views: 498
how to get started with cpld/fpga?
hi all,this is not a new question but my experience about cpld/fpga is almost zero. all concepts and comments that you discuss here are very new for me. so can someone show me some ways to get closer?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02 Mar 2006 7:18 :: deb_mallik :: Replies: 5 :: Views: 480
questions about termination and pcb layout
hi all, im designing a board which has an fpga xc3s1500 interfacing with qdr sram memories. it works at 100 mhz (effectively 200 mhz because the qdr memory uses both rising and falling edge - ddr). i ...
PCB Routing & Schematic Layout software & Simulation :: 27 Feb 2006 11:22 :: sugvivek :: Replies: 2 :: Views: 324
features of protel dxp 2004?
rdware and software devices features always inactive?3. does it needs support of altera quartus or xilinx ise software to burn codes to fpga devices of those company?4. is there any way to virtual si...
PLD, SPLD, GAL, CPLD, FPGA Design :: 08 Jan 2006 6:20 :: samcheetah :: Replies: 3 :: Views: 348
how to simulate this system? orcad can do? or others?
i want to simulate my system:one virtex4 fpga and some other leds and others, i have all rtl file(writen by verilog) for the virtex4 fpga, and the schematic of the fpga and other parth are aready desi...
Software Problems, Hints and Reviews :: 22 Dec 2005 20:31 :: jhallows :: Replies: 5 :: Views: 438
need advice on building a pci card
i have thought about getting something like this high volume starter kit bundle (hw-spar3-cpld-dk) xilinx development boards fromhttp://www.xilinx.com/xlnx/xebiz/designresources/ip_product_details.js...
PC Programming and Interfacing :: 29 Nov 2005 23:45 :: chiptoxic :: Replies: 7 :: Views: 1161
urgent need for 4-layer fpga based pcb design and implement
ar members,i am in an urgent need for pcb design and implementation services for an fpga board with xilinx spartan-3 xc3s1500fg676. my budget is very limited. my complete need is:1. schematic design2....
PCB Routing & Schematic Layout software & Simulation :: 29 Jun 2005 13:34 :: Mazi3 :: Replies: 2 :: Views: 198
what is a function of pll and dll in fpga ??
hi..what is a function of pll and dll in fpga.. while selecting fpga... which specifications related to pll and dll i should keep in mind.can anyone give me some example where pll and dlls have playe...
ASIC Design Methodologies & Tools (Digital) :: 22 Jun 2005 8:06 :: dBUGGER :: Replies: 7 :: Views: 1491
how can i find rise/fall time of xilinx fpga?
how can i find rise and fall time of output signals from xilinx fpga ? will it generate any file after synthesis which will provide this sinformation ?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Jun 2005 14:31 :: power-twq :: Replies: 5 :: Views: 372
which is the first company that produce fpga?
q1.why fpga can guarantee almost all logic design can be implemented in its le( logic cell/logic cell), base on what theorem?q2.who is the le(fpga) invetor, which paper(s) is fpga pioneer paper?q...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Jun 2005 7:23 :: power-twq :: Replies: 4 :: Views: 243
fpga
what is fpga and what for?...
Electronic Elementary Questions :: 16 Mar 2005 16:11 :: kairimai :: Replies: 17 :: Views: 1557
how to protect the bitstream in xilinx/altera fpga?
actel have some fuse and flash base fpga that can protect the bitstream inf fpga device . does xilinx or altera have similiar function or devices?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Feb 2005 7:18 :: alixedi :: Replies: 12 :: Views: 823
i need job in germany.
i need job in germany.fpga/cpld altera xilinx picavrarmpcb and more.ka_ru2003@msn.com...
EDA Jobs, Promotions, Advertising :: 18 Nov 2004 12:39 :: ep20k :: Replies: 14 :: Views: 2207
how to start with xilinx's fpgas
robably this question is very banal but i would like to create a pcb as simple as possible with one xilinx fpga lat say from spartan family.i would like to create a simple download cable as well.as a ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10 Nov 2004 3:09 :: nj_jack :: Replies: 9 :: Views: 573
how to configurate a xilinx device with a mcu and flash?
to gain lower cost and less pcb area , i need to configurate the xilinx device -spartan 3 with the mcu and flash memory ,but i dont know how to do it.somebody knows ?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 24 Sep 2004 8:47 :: 5life :: Replies: 8 :: Views: 714
p*otel 2004 update?
hi all, is somewhere available update from dxp to 2004?...
PCB Routing & Schematic Layout software & Simulation :: 17 Aug 2004 19:03 :: Frosty :: Replies: 6 :: Views: 855
highest bga pin
hi i would like to know the highest no of bga pins that anyone have succesfully routed and may i knoe what is the name of the i/c & whats it use for?regardstaring...
PCB Routing & Schematic Layout software & Simulation :: 29 Jul 2004 12:53 :: majnoon :: Replies: 8 :: Views: 924
board level design
i was wondering if anyone out there doing this stuff can tell me 1) what skills are required for am fpga board level design2) what tools?3) whats the neccesary background?i am quite comfortable with t...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07 Jul 2004 17:55 :: delay :: Replies: 4 :: Views: 1107
spartan2 &jtag& pcb design? thx!!
how to design the jtag interface of a fpga system?in this system ,one spartan2e chip was used!!!!!may u give me some advice when i design the pcb ?thanks!! :?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10 Jun 2004 13:24 :: echo47 :: Replies: 1 :: Views: 327
hold time issue!!??
hi all,i understand that hold time violation happens when the data retain too short after the active edge...but what about, say the data retain for 2 clock cycle, but it falls on the 2nd active edge, ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Jan 2004 5:03 :: andromeda :: Replies: 10 :: Views: 1774
spartan 2 configuration method
hi all,what is for you the best, simplest, cheapest method to configure a spartan ii ?please describe your method (pc cable and software , configuration device used on board, ...)thx :please:...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Dec 2003 13:24 :: Git :: Replies: 6 :: Views: 1151
about xilinx programming eprom and spartan 2 fpga
hello:this is my first time to use xilinx fpga.i had designed the pcb , now i want to test my code is correct,so i have to program the code to the xilinx eprom .i have question about programming , i u...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Jan 2003 13:32 :: Bartart :: Replies: 1 :: Views: 1256
xilinx spartan ii eval-board
hi,i am looking for an eval-board with a xilinx spartan ii fpga. it schold be cheap and flexible in the way of use. thanks for any linksolpa...
Hobby Circuits and Small Projects Problems :: 24 Sep 2002 1:50 :: al_extreme :: Replies: 8 :: Views: 4039
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