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clock divider by 3 with 50% duty cycle?
hi all,how to build a clock divider by 3 with 50% duty cycle?input and output are listed below.clkin__--__--__--__--__--__--clkout______------______------any suggestions will be appreciated!best regar...
ASIC Design Methodologies & Tools (Digital) :: 17 Jul 2007 13:50 :: jasmine25 :: Replies: 27 :: Views: 5937
qam demapping to ldpc decoder
hi all,ldpc decoder use soft information. but how to get the soft information from qam?btw, dvb-s2 use ask demapping, is it suitable for soft information demapping?best regards,davy...
Digital communication :: 02 May 2007 17:35 :: mar-cas1 :: Replies: 6 :: Views: 789
how to simulate netlist with gated clock?
hi all,when i simulate netlist (verilog style) with gated clock, i found the output is very different with what i see in rtl level (with a lot of red xxxx).so i add tfile in ncsim to forbidden the del...
ASIC Design Methodologies & Tools (Digital) :: 13 Apr 2007 9:03 :: sumit_techkgp :: Replies: 12 :: Views: 762
[dc] determine parameter in set_input_delay?
hi all,when use set_input_delay/set_output_delay, how to determine the -max/-min parameter? is it calculated by hand , calculated by tools, or give out by some standard specification?set_input_delay -...
ASIC Design Methodologies & Tools (Digital) :: 27 Feb 2007 18:29 :: shiv_emf :: Replies: 7 :: Views: 249
matlab rayleigh fading channel simulation?
hi all,i have got a rayleigh fading channel simulation code by matlab.the code list below:% rayleigh fadinga = sqrt(0.5)*( randn( 1, symbols_per_frame) + j*randn( 1, symbols_per_frame) );% complex noi...
Digital communication :: 05 Feb 2007 0:21 :: waqasbukhari :: Replies: 16 :: Views: 5400
systemverilog behavioral model?
dear all,i have try to use systemverilog for 3 month of the year.is there any open simple systemverilog behavioral model that we can learn from.any suggestions are welcome!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 15 Dec 2006 12:24 :: Guru59 :: Replies: 2 :: Views: 174
systemverilog clocking block assign data time?
hi all,i use clocking block to construct testbench component like driver.and i am confused with what time clocking block to synchronize data.for example, there is sync_fifo_if_i interface instance and...
ASIC Design Methodologies & Tools (Digital) :: 08 Dec 2006 2:07 :: davyzhu :: Replies: 3 :: Views: 117
verilog problem: default case to set signal xxxx
hi all,i always found people like to add default branch like below:case(branch) ... ... [all the possible branch] ... ...default: signal = 8bx;and my friend told me its for simu...
ASIC Design Methodologies & Tools (Digital) :: 27 Nov 2006 4:30 :: echo47 :: Replies: 6 :: Views: 144
[ncsim] stop -> force -> run error?
hi all,i want to write a tcl in ncsim to do below work.1. stop when $signal is 12. set the lock to force stop only stop once3. force $other_signal4. continue run5. force $other_signal back6 continue r...
ASIC Design Methodologies & Tools (Digital) :: 25 Sep 2006 6:08 :: aji_vlsi :: Replies: 6 :: Views: 492
concatenate string in verilog?
hi all,i want to open a lot of files and read data to reg.something like//-----code--------$readmemh(.\pattern\0.dat,inmem0);$readmemh(.\pattern\1.dat,inmem1);...$readmemh(.\pattern\49.dat,inmem49);//...
ASIC Design Methodologies & Tools (Digital) :: 01 Apr 2006 8:06 :: aji_vlsi :: Replies: 3 :: Views: 726
how to write compact dff chain?
hi all,sometimes i have to write long dff chain like below://------code--------------...reg [7:0] dff0,dff1,dff2,...dff50;always@(posedge clk) if(rst) begin df...
ASIC Design Methodologies & Tools (Digital) :: 27 Mar 2006 2:50 :: linuxluo :: Replies: 4 :: Views: 174
matlab how to do z=f(x,y)?
hi all,i want to do x=;y=;z=log(exp(x)+exp(y)); i want to get z as a 101*101 (n*n) vectorbut the matlab give z as a 1*101 (1*n) vector.how to get z 101*101 vector without for loop?best regards,davy...
Electronic Elementary Questions :: 19 Mar 2006 9:44 :: neils_arm_strong :: Replies: 3 :: Views: 117
what's ncverilog snapshot mean?
hi all,i used to be a modelsim user. now my boss force me to use ncverilog(seems very difficult to learn). we dump data from ncverilog and view signal using debussy. all controled by script.whats sna...
ASIC Design Methodologies & Tools (Digital) :: 14 Feb 2006 2:51 :: kgeorge123 :: Replies: 7 :: Views: 975
compile and elaborate?
hi all,i am new to candence tools. whats the difference with compile and elaborate?and where can i download the manual of the candence tools?best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 21 Dec 2005 7:16 :: xworld2008 :: Replies: 2 :: Views: 195
"analog" ram and d-filpflop?
hi all,we know that digital circuit use ram and d-ff to store digital signal values. is there any analog ram and d-ff which can store analog signal values?i am curious to know if not, how to store ana...
Electronic Elementary Questions :: 22 Nov 2005 22:26 :: Sceadwian :: Replies: 6 :: Views: 312
what's one-wait-state on-chip rom mean in ti?
hello all,i am reading tis datasheet. and whats one-wait-state on-chip rom mean? can it be reprogrammable like flash?any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 29 Sep 2005 7:40 :: puviarasu :: Replies: 6 :: Views: 198
mpeg2 mp(at)ll and mpeg1?
hi all,i heard that mpeg2 and mpeg1 use same compression methods.mpeg2s mp@ll and mpeg1 are all 4:2:0, 352*288*30. but mpeg2s mp@ll is 4mbit/s and mpeg1 is 1.5mbit/s. why they have different bit rates...
Digital Signal Processing :: 06 Sep 2005 8:53 :: swahlah :: Replies: 1 :: Views: 177
[verilog] how to read data from a file?
hi all,i want to read one data per clock from a flie, and send them to a pipelined circuit.after that, save one data per clock to a file.i am new to testbench. now i decide to read a data (in) from fi...
ASIC Design Methodologies & Tools (Digital) :: 10 Jul 2005 17:05 :: jarodz :: Replies: 3 :: Views: 429
[verilog] how to save data to a file?
hi all,i want to save data to a file. and i use $fopen, %fwrite, %fclose. but i found these function only can be called in initial block. when i use them outside initial block, the compiler report err...
ASIC Design Methodologies & Tools (Digital) :: 07 Jul 2005 2:55 :: jjww110 :: Replies: 7 :: Views: 2010
how about signed adder?
hi all,i want to add two 6 bits signed digit. something like 6b10_0110, the msb 1 is negative digit,other00100 is absolute value.or something like 6b00_0110, the msb 0 is positive digit,other00100 is ...
ASIC Design Methodologies & Tools (Digital) :: 29 Jun 2005 14:12 :: AlexWan :: Replies: 6 :: Views: 537
1*512m vs 2*256m ddr ram?
hi all,i want to buy a new pc. and 1*512m and 2*256m ddr ram, which better?from the performance aspect and why?any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 22 Jun 2005 14:40 :: power-twq :: Replies: 7 :: Views: 339
bch code length must be 2^m -1 ??
hello all,matlab supply the bchenc function, but it said the code length must be 2^m -1.could code length not equal to 2^m -1? any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 23 May 2005 16:52 :: zorro :: Replies: 1 :: Views: 318
'signal' (vhdl) = 'wire' or 'reg' (verilog)
hello all,i found vhdl use signal and verilog use wire and reg to describe a connection between combinational logic, but the thing bothered me that how to specify the signal to be wire or reg or sign...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Oct 2004 5:01 :: bibo1978 :: Replies: 4 :: Views: 921
telephone cable voltage
hello all,how about the telephone cable voltage?regards,davy zhu...
Electronic Elementary Questions :: 27 Aug 2004 5:10 :: delay :: Replies: 5 :: Views: 918
ti resource cd??
hello all,how to apply for the tis resource cd on tis website?regards,davy zhu...
Digital Signal Processing :: 26 Aug 2004 12:35 :: dora :: Replies: 1 :: Views: 342
search asy sram controller(verilog)
hello all,can you give me some ref code or site on asynchronous sram controller by verilog?btw, i have searched opencores, but its controller is by vhdl.regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Aug 2004 12:48 :: wadaye :: Replies: 3 :: Views: 414
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