How to design a buffer to drive a wire of 1500 to 3000um

Anyone knows of any buffer design to drive a wire of 1500 to 3000um in length?

Many Thanks in advance

at what frequency?

analog or digital?

It is in digital.........at a clock frequency of around 1GHz......Pls advice. Thank you.

Is 1500 to 3000um is the total length of a wire, or the diameter of the wire?

1500 to 3000um is the total length of the wire.

I think you mean by micro=1*1exp-6
So for 1500um wire=1500/1000000=0.0015meter=0.15 Centimeter

This length is very small. I hope I have understood this in the correct way.Please tell me, first about this.

Yes. It is 0.15cm

What two circuits are connected at two ends of this wire? Are you sure you need to have a buffer for length this small?

I am afraid that I do not get what you mean.....Pls explain.

buffers drive RC loads (capacitance is usually the main hit), not distance. We are assumming that the 0.15cm wire actualls connects to something, and this something will have a capacitance and a resistance.

Inductance or capacitance to ground of 3mm wire is very low, and you would not need any buffer for wire itself. Load might be another story.

The connection is as follows: Device A driving device B through a wire of 1500 to 3000um.

Is there a super duper solution to drive this long wire in order to ensure the signal integrity?

OK, for 1GHz, you a have a wavelength of 0.3m. That is 300000um. So, 1500 to 3000um is not long at all. However, being a digital signal means that what you transmit is a square wave. That has higher frequency components with smaller wavelengths. Still 3000um doesn't sound as too much for 1GHz.

Now, what they are saying is that the important thing is how device B is. Well, actually how its input is. Is it capacitive? Is it 50ohm?

My advice is that you just need to know the total C seen at the input of device B, then use a driver for that load.

Good luck!

Initially I do agree but it will take about 3ns for the signal to travel from one end of the wire to the other end of the wire when it changes from logic 0 to 1.

But however, it takes less than 500p-sec to travel from one end of the wire to the other end of the wire when the logic changes from 1 to 0.

I still don't understand why does it take 3ns to travel when the logic changes from 0 to 1 as I have already sized the buffer such that the ratio of PMOS to NMOS is 2:1.

Any advice

About the falling time, 500p doesn't sound too good either for 1GHz, half cycle is 500ps already, so I would make it faster.

About the rising time. It could very well be that the ratio you need is larger than 2. You may need 4:1 or more.

I would go for a bigger NMOS and a much bigger PMOS.

I very much doubt that signal travels 3ns along 3mm wire. Time of travel will be just a tad longer then 3/3E11 [mm/mm/s]or 10ps. Your "B" device has high capacitance and your driver ("A" device) can't supply enough current to drive input capacitance of device "B" . It has nothing to do with your 3mm wire. If you look at the scope you will probably see that signal is not delayed but distorted, you get ramp instead of sharp edge.
A lot of times nubies like yourself would make mistake in measurement as well, so let us know how did you get to this information of "delay", how waveform looks like. Getting info from you feels like pulling your teeth out.

If you are asking somebody to help you, disclose all information you have available. Don't waste our time. Also, there are several people here that say same thing and you disagree. If you already made your mind, why did you ask?

You are correct to say that. It is like a saw tooth waveform.......charging up slowly and discharging at a faster rate. Any idea how to resolve this issue?

Well I also think that those figures are a little bit too slow, for 3ns if the signal is 1.8V, a capacitive load of 2pF would require 1.2mA. To be honest, something below 2pF doesn't sound too difficult to get and something over 1.2mA sounds really easy.

I'm sorry but I have to agree with Sinisa, you are not giving too much information. See how many times I have had to assume some data that I actually don't know. Why don't you explain it a bit more so you make it easier for everyone?

My apology if I am not that precise. So, based on the scenarios that I have given so far, what are the info that are required?

Ok, first what is device "A" and "B", it's type, part #,...? What are you using to measure signal at the input of device "B", if it's oscilloscope, what kind of probe are you using? Do you know input capacitance of your device "B", capacitance of oscilloscope probe (if that is used) and both source and sink current capability of output of your device "A"? What is your power supply, and what is signal level? Is this IC design or you are making circuit from components? Is clock single sided or differential?

There are huge number od clock driver IC that you could use, e.g. https://www.onsemi.com/PowerSolutions/parametrics.do?id=112

Generally speaking, your clock signal has to charge input capacitance of your "B" device from low logic level (VL) to high logic level (VH) and back to low logic level (VL) in less time than 1 clock cycle or 1ns. In other words, charging time and discharging time of device "B" input capacitance between VL-VH-VL together has to be shorter than total clock cycle time. VH and VL are determined by your "B" device and it's power supply.

So device "A" minimum output current capability requirement will be:

I = 2fC(VH-VL)

This is if sink and source currents are same. Make note that you need to go higher than that to have some room for other type of errors.

You can easily calculate requirement for sink and source currents and you can measure total capacitance of probe and input of "B" device from dU, dt and separately measured output current capability of A device.

So now, if this is not clear, dont spare your fingers from keyboard and put as much information as you have that might be relevant.