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Design Synchronous MOD-5 counter.

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kumar91

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Design a MOD-5 synchronous counter using J-K flip flop...????
espically i want excitation table of counter.
 

This is simple use a 3 bit sync counter with a little modification that the CLR pulse is an inverted output of the 3 rd JK flip flop
 

but in case of synchronous counter we dont use CLR. That's why i'm asking abt unused states which will create condition of LOCK OUT...what will be the next state for these states...
 

No problem with them friend just count on till it counts 4 which is 100 then instead of 101 (5) the outputs of 1st and 3rd ff are NAND and fed to the CLR pins of the 3 FF this resets them and starts the count from 000 to satiate your need


PS I made a small error in my first post and have rectified it here do check it up

- - - Updated - - -

Instead of going for other designs this is best suited
 

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