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adding flops ( pipelining) to meet timing in backend

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jaya sree

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hai ,

generally if data delay is much more than clock period , that path is declared as multi cycle path .Then why to do break that path ( do pipelining ) and add flops to meet timing.Please explain in detail.

thank you
jaya sree
 

Suppose your combo logic takes 10 ns to complete an operation and lets assume the clock to be of timeperiod 5ns .In this scenario we have to break the combo logic into 2 halves lets say each takes 5 ns.In the first 5 nano second one part of the combologic is completed ,so we will register to a flop and in the next 5 ns second half of the combo logic completes and we will register this .After this process we will combine the outputs of the 2 flops which act as the actual output of the combo block.
jaya sree said:
hai ,

generally if data delay is much more than clock period , that path is declared as multi cycle path .Then why to do break that path ( do pipelining ) and add flops to meet timing.Please explain in detail.

thank you
jaya sree
Click to expand...
 
jaya sree said:
hai ,

generally if data delay is much more than clock period , that path is declared as multi cycle path .Then why to do break that path ( do pipelining ) and add flops to meet timing.Please explain in detail.

thank you
jaya sree
Click to expand...

Jaya, What is the value addition with this approach? Any way you will have the same path with an additional flop resulting in added area and power. No advantage in timing view point.
 
hi jeevan Area will increase thats true but it will help in timing...jeevan please read and analyse my previous thread properly.............
jeevan.life said:
Jaya, What is the value addition with this approach? Any way you will have the same path with an additional flop resulting in added area and power. No advantage in timing view point.
Click to expand...
 
o.k . i understood. but that path can be declared as multicycle path right ? whats the need to go for flop insertion.
 

data path is identified as multi cycle path, only when the target logic consume data after two/three clocks. usually flop will not be inserted to meet timing.

Please anyone confirm whether my understanding is correct or not.
 

dll_fpga said:
Suppose your combo logic takes 10 ns to complete an operation and lets assume the clock to be of timeperiod 5ns .In this scenario we have to break the combo logic into 2 halves lets say each takes 5 ns.In the first 5 nano second one part of the combologic is completed ,so we will register to a flop and in the next 5 ns second half of the combo logic completes and we will register this .After this process we will combine the outputs of the 2 flops which act as the actual output of the combo block.
Click to expand...

This holds good for a certain set of cases but not all the cases. If you have complex cells and multiple inputs coming in its not very easy to split the path into two.

Also , Multicycle path can exist if launch FF is clocked by clock x and captured by clock y, where in the frequency of y is higher than frequency of x.
 
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