DE4User
Junior Member level 2
Hi All,
I am wondering what is the delay for a AND (OR,NOT) gate in latest ASIC technology? and what about a typical flip-flop? The reason I ask is I want to
calculate the delay of my digital design by hand, thanks.
I am wondering what is the delay for a AND (OR,NOT) gate in latest ASIC technology? and what about a typical flip-flop? The reason I ask is I want to
calculate the delay of my digital design by hand, thanks.