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question regards to the delay of basic digital components

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Hi All,

I am wondering what is the delay for a AND (OR,NOT) gate in latest ASIC technology? and what about a typical flip-flop? The reason I ask is I want to
calculate the delay of my digital design by hand, thanks.
 

If you mean the propagation delay even for a certain design process there a different libraries to consider. Here I can give only the propagation delay of the 65 nm lpsvt process. For the AND2 the delay is from 25 to 40 ps, for the OR it is from 25 from 45 ps, for the NOT it is 10 ps.
The CLK to Q of the TSPC DFF is 60 ps.
 
Thank you so much! Could you tell me where can I get those information? Is there any website or literature?
 

Hi AdvaRes,

Do you know the propagation delay for AND3 and OR4 under 65nm lpsvt fabrication process? By the way, could you tell me how to calculate the propagation depay based on the pdf you provided? Since the pdf just gives the propagation delay of inverter. Thank you so much!
 

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