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Doubt in Timing and optimization controles setup

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sharif.shiek

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Hi everybody,

In physical design flow, after completion of data setup, before going to Implementation we set some timing and optimization controls, in that we enable constant net buffering control as TRUE, what happen if we set this as false..?
 

I think you mix many idea, the constant net optimization could be done directly at the first synthesis and after the physical aspect (floor plan, topology) could be included...
 

rca said:
I think you mix many idea, the constant net optimization could be done directly at the first synthesis and after the physical aspect (floor plan, topology) could be included...
Click to expand...

oh sorry, In IC compiler we enable constant propagation..what is it?
 

Hi Sharif,

Constant propagation helps your tool to reduce the runtime and avoid false violations during timing analysis...for eg your reset/enable signal which which will be held at constant value in a particular mode should not be analyzed for all the cases...when you know that particular signal will be held at a constant value throughout.

cheers,
 
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