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From the layout structure the tool will identify the transistors, recognize cell, memories and interconnection to construct a net list , and will compare this netlist with the netlist generated from the schematic or the netlist created from the version.
It is compared point by point, net by net and transistor by transistor (no any logical equations). Yes, some minor differencies between these two netlists are allowed (like merging parallel transistors in one big: in schematic you have one tran, in layout the tran is represented by some fingers, that in sum gives the same length and width of cmos gate).
They both are supposed to be always the same.i mean always they both are different na?
They both are supposed to be always the same.
ya, but after getting netlist, in the process of generating GDSII (layout) we are doing many modifications like optimizations and buffer insertions and gate sizing and all those will cause to differentiate the layout from original netlist, then how can we compare those two..i mean always they both are different na?
At the same time you are generating GDS, you should generate the new netlist, and you will compare the GDS with this new netlist (which was modified). The LVS will prove, that GDS and netlist are equivalent (point by point). In order to be sure, that final GDS is logically equivalent to initial netlist, you must run Formal verification between initial netlist and the final netlist. So, if init_netl==final_netl (by formal_verif) AND final_netl==final_gds (by LVS), then init_netl==final_gds. Or differently init_netll == final_netl == final_GDS. It is usual flow, there are several different flows like: use functional simulation rather the formal verification (no 100% guarantee); use derived from GDS netlist as one of inputs netlist to formal verification...