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3-terminal capacitor in CMOS process : vncap vs vncap_inh

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wighou

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Hi,

I use the IBM CMOS8RF design kit. In capacitor library, there's a vertical natural capacitor, with two versions : vncap and vncap_inh. The first has 3 terminals, the second has 2 terminals. When I don't use the third terminal, the result is the same as the for vncap_inh.

In the vncap, what the third terminal stand for ?
I have the same problem with MIMCap.

Regards,
wighou
 

Re: 3-terminal capacitor in CMOS process : vncap vs vncap_in

Thanks for your answer oermens.
The capacitor has 2 options to model parasitic capacitors. It can be over substrate or over n-well. So the third port is substrate or n-well, isn't it ?
Other question, when the third terminal is not connected (equivalent to vncap_inh), does it signify that parasitic capacitors are not token into account ?

Regards,
wighou
 

I don't have those libraries, but the other possibility is that one of the capacitors is a sandwich capacitor i.e. three plates with the middle top and bottom ones normally connected. There should be some documentation with the libraries explaining what they are, or in the header of the library itself.

Keith.
 
Re: 3-terminal capacitor in CMOS process : vncap vs vncap_in

The first thing I did is to read the documentation. But there's no answer to a such trivial question. This kind of document is addressed to experienced user. So, I didn't find indication for the symbol terminals. It's the first IC I will design and I have a lot of doubts for all steps of my design. Which kind of capacitor, inductor, level of metal, (...) I have to use ? How to make transmission line, coplanar, microstrip ?
So, you may see a lot of dummy questions from me in this forum ...
 

Re: 3-terminal capacitor in CMOS process : vncap vs vncap_in

I don't have this document. I have the cmrf8sf_design_manual that does not contain this kind of information.
 

it is in the cdslib/doc folder.

edit: don't bother it doesn't explain anything. you need to read the 8rf training guide, available from mosis doc server (if you are a customer) or thru ibm.
 

Re: 3-terminal capacitor in CMOS process : vncap vs vncap_in

I really don't have this document. In my cdslib/doc folder, I just have a release notes pdf.
But, it's true the training guide is interesting.
 

Hi there,

I also got the same unsure thing,

I used the GlobalFoundies, and the capacitor have three terminal, but no doc mentions that.

I know its subtract, but should connect it to vdd or gnd?

Rgs

Tdf
 

Pls check layout cell from PDK for device structure. For MIM cap, the 3rd terminal should be p-sub.
For capacitance, pls check your model file.
 

Hi fellows,

I have one question regarding the same problem. If the capacitor has 3 terminal T1, T2, and suIs there any harm in connecting the capacitor substrate to T2 for example?

The reason for this because when doing so in the schematic, my circuit performs its function well.
 

I have a problem here in 3-terminal capacitors. If I connect the bulk to terminal 2 for example and this terminal is not connected to GND I will get multiple stamped connection problem.
Also I have a transistor that its bulk is connected to something but not GND. This also causes multiple stamped connection problem. Anybody can help?
 

khaled2k said:
I have a problem here in 3-terminal capacitors. If I connect the bulk to terminal 2 for example and this terminal is not connected to GND I will get multiple stamped connection problem.
Click to expand...
Bulk must be connected to GND.

khaled2k said:
Also I have a transistor that its bulk is connected to something but not GND. This also causes multiple stamped connection problem.
Click to expand...
Is it an NMOS? If so, its bulk also must be connected to GND (if it's not a double||twin||triple well process).
 

erikl said:
Bulk must be connected to GND.

.
Click to expand...

I didnt get it. If I have three terminals capacitor and want to connect 2 terminals together (and not to GND).
Is this possible? You said in another post that it is possible.
 
Last edited:

If I have three terminals capacitor and want to connect 2 terminals together (and not to GND).Is this possible?
Click to expand...

My opinion is negative to this...The third terminal of a process capacitor should be always connected to sub!

If your process doesn't include or support a model for the interface of p-substrate (sub!) and ground (VEE/GND) such as subc in various IBM's technologies then you should connect the third terminal to VEE.Now,suppose that you have somewhere in your schematic a cap from a node X to VEE.In this case you can short-circuit the two common terminals of the capacitor and connect them to VEE.I suppose erikl was implying this case when said yes above.
 
Last edited:
khaled2k said:
I didnt get it. If I have three terminals capacitor and want to connect 2 terminals together (and not to GND). Is this possible? You said in another post that it is possible.
Click to expand...

Let's assume the 2 active terminals of the device are T1 & T2, the 3rd terminal "BULK" concerns the substrate below this device. If the device is over the substrate (p doped), BULK must be connected to substrate resp. GND. Same if the device is in a separate n-well and this n-well is connected to GND. (Some processes allow devices being assembled together with PMOSFETs, in this case the n-well usually is connected to VDD or some lower voltage level, and in this case the device's BULK terminal is to be connected to the n-well (potential) and not to GND).

In that other post I said you can of course connect one of the (active) device terminals (T1 or T2) -- or both -- to substrate -- same as BULK.
 

jimito13 said:
My opinion is negative to this...The third terminal of a process capacitor should be always connected to sub!

If your process doesn't include or support a model for the interface of p-substrate (sub!) and ground (VEE/GND) such as subc in various IBM's technologies then you should connect the third terminal to VEE.Now,suppose that you have somewhere in your schematic a cap from a node X to VEE.In this case you can short-circuit the two common terminals of the capacitor and connect them to VEE.I suppose erikl was implying this case when said yes above.
Click to expand...

Thank you jimito for your reply
In my process, the schematic has 3 terminals. In layout two terminals and I have to create PD_C to connect the substrate.
Now I have another question, If I left the substrate node in the schematic floating and I still have the expected simulation results, is there any problem?
 

In my process, the schematic has 3 terminals. In layout two terminals and I have to create PD_C to connect the substrate.
Click to expand...

I don't know the process you use so i can't absolutely say where is the correct termination (sub or gnd) of the third terminal of your cap.So,take a look
at the tech manuals and see their instructions or furthermore contact your pdk support for more help.

Now I have another question, If I left the substrate node in the schematic floating and I still have the expected simulation results, is there any problem?
Click to expand...

The answer is NO definetely.Your thought is just a "cooking" of the results...Try to come to the expected results via the correct way and not with cheating ;-)
 

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