How to bundle signals in VHDL

childs said:

Hi, I am working on VHDL code where I wish to bundle certain parts of a std_logic_vector signals for readability purpose. A simplified demonstration of my design is as follow:

Code:

signal data: std_logic_vector(15 downto 0);   --data(15 downto 8) is data_part_1; data(7 downto 0) is data_part_2
......

instead of:

Code:

if (data(15 downto 8) = x"ff) then
...... (work on part 1)
if (data(7 downto 0) = x"55") then
...... (work on part 2)

I wish to make my code more readable by:

Code:

if (data_part_1 = x"ff") then
...... (work on part 1)
if (data_part_2 = x"55") then
...... (work on part 2)

Assigning data into signals data_part_1 & data_part_2 will need another clock cycle. My current implementation is assign using variables as below, may I know such whether this is appropriate for design to be synthesized? Is there a better or more appropriate way to do this?

Code:

data_part_1 := data(15 downto 8);
data_part_2 := data(7 downto 0);

Thanks!

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