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Preliminary Question in an ADC terminlogy

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santom

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Hi,
I have got a very basic doubt suddenly.Thought I should ask you people here so that I get cleared and also others in future if they are equally confused like how I am now

In a 10 bit SAR ADC, for example if the sampling frequency is 2 KHz, then the entire conversion cycle takes place in 11 clock cycles(including reset phase as well) and so the internal clock frequency should be 11 times faster(22 KHz)

My question is, is it then we should give a 1 KHz input signal to test the ADC as the sampling frequency set is 2 KHz in order to obey the sampling theorem.

Or Am I wrong... Help me people. Thanks a bunch

Peace out
Santom
 

Your numbers are correct, assuming that 1 internal clock cycle provides enough time for overhead such as reset and output data transfer.
 
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    santom

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thanks ..but is it possible to take 12 times faster clock too? i mean , can i use 12 clock cycles instead of 11 clock cycles for one conversion cycle?
 

You can use a faster clock. The important thing is that the conversion is fast enough to allow at least 2 samples for each cycle of the the highest frequency input signal of interest.
 

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