[SOLVED] two Level FIFO Design on Virtex 5 FPGA

Hi I'm designing a two level fifo for a HS-ADC on a Virtex -5 FPGA one for ADC FIFO and another is for Power Processor(PPC) FIFO. I have width of 32bits and depth of 1024.
ADC FIFO works on the clock synthesizer frequency(ie 245MHz) and is async FIFO with read domain works at 100MHz and PPC FIFO is Sync FIFO and works at 100MHz.
when I run u-boot and read the HS-ADC digital value from PPC FIFO at 245MHz all 1024 values are obtained. But when I change to the lesser frequency ie @ 163MHz only 740 values are obtained.
can any one help me on this as i have verified using chipscope too.

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Regards
Pratima

Are you overrunning your fifo? If you're writing at 245MHz and reading at 163, then at some point the fifo will fill up and overrun.

I don't quite understand how these fifos are connected, can you give us a diagram?

Thanks Barry,
No, I'm not over running FIFO, I have attached you with the connection diagram and the instantiation of the both FIFO.

1.There are two clocks, 1st fpga_adc_dclk_i which is generated from the external clock synthesizer and 2nd clk_i which is generated inside FPGA.

2.There are two cases, in first case the fpga_adc_dclk_i is set to 245MHz and clk_i is 100MHz and when i see output on hyperterminal there are no
missing data, with all 1024 values from the adc.

3.In second case the fpga_adc_dclk_i is set to 163MHz and clk_i is 100MHz and there are some missing data, only 740 data's are coming.

4.Here is the instantiation
//Independent Clock Block RAM Type FIFO
//First Word Fall Through FIFO
//Size 1Kx32
//Full Flag Reset Value 0
hsadc_fifo hsadc_fifo
(
.rst (rst_i ),
.wr_clk (fpga_adc_dclk_i ),
.rd_clk (clk_i ),
.din ({2'b00,hsadc_chb_data,2'b00,hsadc_cha_data}),
.wr_en (hsadc_fifo_wr ),
.rd_en (adcfifo_rd ),
.dout (adcfifo_rddata ),
.full (adc_fifo_full ),
.empty (adc_fifo_empty )
);

//Common Clock Block RAM Type FIFO
//Standard FIFO
//Size 1Kx32
//Full Flag Reset Value 0
//Data count sync with clock, UnderFlow flag,
//Programmable Flag, Single Programmable Full threshold input port enabled
hsadc_ppc_fifo ppc_hsadc_fifo
(
.clk (clk_i ),
.rst (ppc_fifo_rst| rst_i ),
.din (adcfifo_rddata ),
.wr_en (ppcfifo_wr ),
.rd_en (ppc_fifo_mrd ),
.prog_full_thresh (ppc_fifo_water_mark ),
.dout (ppc_mem_data_o ),
.full (ppc_fifo_full ),
.underflow (ppc_fifo_underflow ),
.empty (ppc_fifo_empty ),
.data_count (ppc_fifo_data_count ),
.prog_full (ppc_fifo_prog_full )
);

If your design is setup to write 1024 words at 245MHz into the FIFO, then when you lower the write clock frequency to 163MHz lesser number of words will be written into the FIFO. You should get around 650-750 words in the FIFO at that frequency. Try changing the write frequency from 163 to 200 and see if the number of words written increases... if so.. then this is the case.

But i need to work at 163MHz with obtaining all the 1024 values so is there any method which i could make use.
This is because iam changing the synthesizer chip on new design which works on 193MHz.
In the old synthesizer works on 495MHz VCXO and i can use divide by 2 or divide by 3 clock only for adc chip on the board.

Well,

If you want to scale down the write clock and still get the 1024 words written into the FIFO,you will have to wait for the FIFO to get full and then only read it. reading before the FIFO gets full will only result in lesser no of words read back. To do this, I suggest you monitor the FIFO full and empty flags , read from the fifo only when the full flag is asserted and write into the fifo when the empty flag is asserted. By doing this you are making sure that the FIFO is full with 1024 words before reading from it at 100MHz.

I believe you can also implement the fifo with a "number of words" output, so you can tell when you've got the desired amount loaded. Or you could keep track externally.

Thanks you, I will do it and reply you back when i get all 1024 data's.
I have also taken wr_data_count and rd_data_count to verify.

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regards

---------- Post added at 10:11 ---------- Previous post was at 10:08 ----------

yeh, that's why i have taken wr_data_count and rd_data_count at the adc fifo to verify how many data are coming in at 163Mhz and going out at 100MHz.

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regards