soloktanjung
Full Member level 6
Hello,
I generate a dual port sram using Artisan, then converted to .db file, set search_path and link_library pointed to the sram, and instantiated in my verilog code. I am using synopsys design compiler.
But I got large timing violation problems on the CLKA and CLKB port of the memory. When I looked using "timing analyzer" as shown in the picture attached, there is a weird component that cause the large delay.
Can anyone please tell me what is the component, and what is the problem?
Thanks in advance.
Best,
Hairo
I generate a dual port sram using Artisan, then converted to .db file, set search_path and link_library pointed to the sram, and instantiated in my verilog code. I am using synopsys design compiler.
But I got large timing violation problems on the CLKA and CLKB port of the memory. When I looked using "timing analyzer" as shown in the picture attached, there is a weird component that cause the large delay.
Can anyone please tell me what is the component, and what is the problem?
Thanks in advance.
Best,
Hairo