Flow for metal mask functional ECO

I want to do metal mask ECO. There are some changes in RTL , I do not want to resynthesis and PnR instead map the new logic using only the spare cells.

Could anybody share what is right way of doing this both at synthesis and layout stage? Is there any automated way ?

There is no easy automated way. The moment you mention ECO, you are basically trying to manually insert something that the tool doesn't like. Now I don't know what is the "right"-way (tm) of doing it, but here is what I did before:

1. First off, if you want to do a metal-mask only change then synthesis stage is pretty much useless. You can only make this change w/ your layout tool.
2. Second, make damn sure that your new "fixed" logic is working (run all the Functional Verification with the changed RTL)
3. I hoped you have kept some spare cells (or GACC) cells lying around. Now what you need to do is go into the netlist file and manually try to make the corresponding RTL change in gates. (Note: you can do this in DC with tcl commands, but I find it easier to just modify the gates file directly)
4. Now you take the modified netlist and you run that through your functional verification test suite (using structural sims). This is to make sure that fixed it correctly.
5. Then, as sign-off run formal verification to verify that the new modified RTL matches the new modified (hand-modified) netlist.
6. Alright, now go into your PnR tool (I am only familiar w/ astro/ICC), open the last design (the design you want to apply the ECO to). Start after the point of Place and CTS, but before Route. Set up the freeze silicon ECO flow (check your manual). Remove the don't touch on your spare cells (set it as soft-fixed). Now insert the new (modified) netlist using the ECO netlist command (eco_netlist in ICC). You will also have to map some spare cells into the new cells. If the change is minor, you can manually change the route by hand (make sure you run DRC). If it is major run the ECO route command (route_zrt_eco / route_eco in ICC).
7. Take it through the rest of the DFM flow.

Well, good luck following that direction I just dashed out of my head w/o looking at the manual.

narfnarf

Thanks narfnarf for detail explanation. You metioned you used ICC, you can help me give some detail about "place_freeze_silicon" command. While modifing the netlist we do not know exact location of spare cells and there is the possibility that may get some timing violations if we choose the spare cells which are placed very far from the desired logic. So my question is does ICC check the timing and then swap the nearby spare cells with the newly added cells , how exactly it works could you please let me know?

you can get the details about the place_freeze_silicon from ICC's user guide. I am not sure I can provide any more details (on specific commands) than the user manual.
As for the spare cells, usually you marked the spare cells as don't touch and/or soft-fixed during the initial place before freeze, so you should definitely know where the spare cells are located...
(it depends on the algorithm you used to place the spare cells, did you place them on a grid array or did you randomly spread them throughout the chip). You can't do ECO w/o knowing what/where your spare cells are located.

If you are worried about timing violation routing to and from the spare cells, ICC tries its best to meet timing when you run eco_route / eco_zrt_route. Of course, you would still have to verify it w/ PT. Generally, you tell ICC which spare cell to use with place_freeze_silicon. If you choose one that is too far then you won't meet timing and ICC / PT will tell you. If you are failing timing, then you can either try a higher strength spare cell (if you have programmable spare cells) or you can try to find a spare cell that is closer. If you still don't meet timing, then either you re-spin the full silicon or try manually routing.

narfnarf