Path, cell and net delay

Hi,
I am
A bit confused with how does the tools (synthesis and implementation) calculate tje delays of nets and cella pre place and route?
And is there a differece between before place and route and after place but before route?

Thanks!

Wow this is an extremely vague question that is hard to answer easily (even in a semester worth of EE class). Quick summary:
1. Before any cell delays/timing can be done, the manufacturer (TSMC, Xilinx, Altera, SMIC, etc...) has to characterize the cells. They do this by ploping down hundreds (if not thousands) of identical cells and measuring its propagation delay, rise / fall time characteristics across multiple PVT (process/voltage/temperature) corners and create a huge array of table look up of propagation delay for every single cell type.
2. Your synthesis tool takes this propagation delay table and create a simplified compressed version of it based solely on fanout and cap load. Then it tries various logic optimizations to get it to meet timing using this simplified delay model.
3. Then your Placer tool take the synthesized netlist and tries to place the actual cell down on silicon and tries to estimate the wire length using various formula (HLPW/steiner tree). This gets it closer to reality (but not quite)
4. finally your Router tries to actually connects the pins of the Std Cells by routing up and down the metal layers (while observing all the possible DRC errors and manufacturing guide lines) and still try to maintain timing.

Yes, a huge difference b/w Post Place and Post PnR. After place you stick don't have any real metal wires (you just have some track usage estimations). After PnR you actually have wires and routes.

narfnarf

Thanks!
That really helped!