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Convert std_logic_vector to natural

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trunkpk

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[SOLVED] Convert std_logic_vector to natural

Hi, i have two std_logic_vector of 5 bits, with these i do a std_logic_vector of 10 bits. I need to convert this 10 bits vector into a natural number, range 0 to 1024.

I want to do this, to introduce the natural number in a rom and obtain the output.

But i have a lot of problems...

This is the code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
ENTITY conver is
 
PORT ( a, b: IN std_logic_vector (4 DOWNTO 0) 
);
END conver;
 
architecture con of conver is
 
SIGNAL aux:  std_logic_vector (9 DOWNTO 0);
SIGNAL aux1:  integer range 0 to 1024;
 
BEGIN
  PROCESS(a, b)
   begin
  
  aux <= a & b;
 
aux1 <= to_integer(unsigned(aux));
 
    end process;
end con;


But doesn't run, and other configurations neither, like conv_integer.

Any suggestion?

Thanks
 
Last edited:

what are Db and Qry? they dont appear anywhere in your code?

You need to add a,b and aux to the process sensitivity list.
 

excuse me, they are a and, b.

The compilation is ok, but when i have simulated, the value of aux1 is 00000 ever.
 

what are a and b set to? have you got a testbench?
 

are you changing a or b only once. since you have used signals inside the process the aux1 will get assigned with a one clock cycle delay. so try something like this in the testbench:

a=16;
b=17;
wait for 10 ns;
a=32;
b=33;
 
oh ***! i've lost two ours in this s***

The problem is that aux1 takes the old value... but i'll solved it, I guess

Thank you very very much :)
 
Last edited:

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