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The change of instance name through synthesis!

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yuanqi

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Hello everyone,

I used the GENERATE statement to instantiate multiple entities in my top level design. After synthesis, the name of every instantiation is added by a backslash at the beginning, shown in the figure. The consequence is that the the names in netlist file are not consistent with those in .SDF file any more. How can I solve that problem? Looking forward your help, thanks!
changed_name.jpg
 

make sure the write_sdf and write -format verilog commands are always used at the same place.

for the [] problem, use these two lines before write
define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
change_name -rules verilog -hierarchy
 
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    yuanqi

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Thanks a lot! It looks promising!
 

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