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[SOLVED] incomplete sensitivity list -- really?

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jlon

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I'm doing a simple Logical Unit module with a few logical functions working on 16-bit values. I want to trigger this logic with a statement run off clocked logic in another module... so I put a "strobe" input and made that the only thing that triggers:
Code: 
module mod_logic_unit (
	input wire strobe,
	input wire [1:0] operation,
	input wire [15:0] opA, opB
	output wire [15:0] result,
	output wire Z, N, S, V
);
	reg [15:0] resultr;		assign result = resultr;
	reg Zr; 			assign Z = Zr;
	reg Nr; 			assign N = Nr;
	reg Sr; 			assign S = Sr;
	reg Vr; 			assign V = Vr;
	
	always @ (strobe)
	begin
		resultr <= 16'h0000;
		case (operation) 
			`LU_AND	: resultr <= opA & opB;
			`LU_OR	: resultr <= opA | opB;
			`LU_XOR	: resultr <= opA ^ opB;
			`LU_NOT	: resultr <= ~opA;
		endcase
		Zr = (resultr == 0) ? 1 : 0;
		Nr = (resultr[15] == 1) ? 1 : 0;
		Vr = 0;
		Sr = Nr ^ Vr ;
	end
endmodule
But Symplify warns of an incomplete sensitivity list... Recently I've learned to heed the synthesizer's warnings, but is this one really valid, given what I mentioned about the design intention, above?
 

Try below code. HTH

Code: 
module mod_logic_unit 
(
  input wire          strobe,
  input wire  [01:00] operation,
  input wire  [15:00] opA, opB
  output wire [15:00] result,
  output wire         Z, N, S, V
);
  reg [15:0] resultr;		assign result = resultr;
  reg Zr; 			assign Z = Zr;
  reg Nr; 			assign N = Nr;
  reg Sr; 			assign S = Sr;
  reg Vr; 			assign V = Vr;

// uncomment appropriate always block declaration based on your signal

//  use below always block, if strobe is asynch signal 
//  always @ (*)
//  use below always block, if strobe is clock signal
  always @ (posedge strobe)
  begin
    resultr <= 16'h0000;
    case (operation) 
      `LU_AND	: resultr <= opA & opB;
      `LU_OR	: resultr <= opA | opB;
      `LU_XOR	: resultr <= opA ^ opB;
      `LU_NOT	: resultr <= ~opA;
    endcase
    Zr = (resultr == 0) ? 1 : 0;
    Nr = (resultr[15] == 1) ? 1 : 0;
    Vr = 0;
    Sr = Nr ^ Vr ;
  end
endmodule
 
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    J

    jlon

    Points: 2
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So, is your intention to trigger this logic on both of positive and negative edge on the single flop ?
 

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