srinpraveen
Member level 2
Hi guys I have a very basic doubt. I want to know how to do this in verilog. I want to do a particular action every xth clock pulse. How do i incorporate this in verilog? Some ppl say I need to use a counter but lets say I need to do a particular action for every 4th rising edge of the clock pulse, then lets say I introduce a counter. The counter counts upto 4. And then the action takes place. But this action takes place at the 4th rising edge of the clk pulse alone. I want the action to get repeated at the 8th rising edge, 12th edge, 16th edge etc...I can't be using x number of counters for this right?
I tried using the mod operator as in if(counter%4==1'b0)....... in a manner we use in C, C++. But as a matter of fact, the mod operator may not throw a simulation error but on the other hand, does not get synthesised in design vision. In other words the mod operator is not synthesisable anyway.
Does everbody understand my question?And if anybody knows about this, can they provide a simple solution to this?
I tried using the mod operator as in if(counter%4==1'b0)....... in a manner we use in C, C++. But as a matter of fact, the mod operator may not throw a simulation error but on the other hand, does not get synthesised in design vision. In other words the mod operator is not synthesisable anyway.
Does everbody understand my question?And if anybody knows about this, can they provide a simple solution to this?