Inputting data to a ram

hello,

I need to input data to a ram .....first 64 bits are inputted to first location of the ram in the first clock cycle....
2nd 64 bits are inputted to second location of the ram in the second clock cycle....
till 8th data at the 8th clockcyle?
i had wrote a code for this in verilog.....but this code is not synthesisable........... here mem is the memory module.........

//////////////////////////////////////

@(posedge clk)
wa =0;
di =mem[addr];
addr=addr+1;
end
repeat(7)
begin
@(posedge clk);
wa = wa+1;
di = mem[addr];
addr = addr+1;
end
////////////////////////////////////


what is to be done so that i can synthesise in fpga? ie.i need to write data to a ram module(not inbuilt Ram but designed by me) in fpga............
first data should go to the first location at the first clock cycle....
2nd data to the second location at the second clock cycle...
and so forth.....
Any psuedo code for the same?....
(if by using chipscope then....tell how this can be achieved....)

You need to make a state machine or something that is triggered by some event such as some signals, releasing reset, etc...

lostinxlation said:

You need to make a state machine or something that is triggered by some event such as some signals, releasing reset, etc...

Click to expand...

hi,
the data i need to input is 64bits wide.....the fpga i'm having only support serial format.....so i was planning to use chipscope.....
do you mean that i need a statemachine wired to my circuit in the topmodule?(in addition to chipscope module)

I'm a bit lost on what you want to do.
You said you want it to be synthesizable so that I thought you just tigger the logic and let the logic to automatically update those memory locations.
Or are you trying to design some interface that can access the memory from the external pins ?

where is the write data comming from ?

BIBINPAUL said:

hi,
the data i need to input is 64bits wide.....the fpga i'm having only support serial format.....so i was planning to use chipscope.....
do you mean that i need a statemachine wired to my circuit in the topmodule?(in addition to chipscope module)

Click to expand...

I had first thought to use a 64 bit data bus....but my FPGA board only has a serial support(but i need 8*(64 bit )data to be inputted).......................

Is there a provision to access a file (.coe) and read the data from that file?

It should be done as below.........
the first 8 bits has to be read in first clock cycle and write it to ram location0....
next 8 bits in next clock cycle to ram loc1...
till 8 th data in 8 th clock cycle to ram loc8....


after 64 clock cycles the entire process must repeat....
but now the data in has to be different(ie values are different from the first 8 values that were loaded in the first 8 clock cycles)...

this process must repeat...................

It is not for simulation but for synthesis....