How to export a deisgn in Cadence Encounter and import to PrimeTime for SSTA signoff?

Is it possible to export a placed&routed deisgn in Cadence Encounter, and import it into PrimeTime, and use PtVx/PtPx engines to re-check timing analysis and power estimation? Thank you.

1) Write out verilog from cadence Encounter
2) write out def from cadence encounder
3) Do extraction using synopsys starxt ( you will need def and .nxtgrd files for extraction) , get the spef file
4) read verilog and spef to primetime and do the required analysis

Reply for finer details

Surprised to see SSTA support in PrimeTime already. Does it need library support? From which version of PT did it begin support SSTA?

I have not used it but synopsys documentation says it supports SSTA

PrimeTime VX
The PrimeTime VX solution extends the PrimeTime environment to analyze device and interconnect variations at 65-nm and below using statistical techniques. Variation-aware analysis with the PrimeTime VX solution delivers improved margin control, avoiding the over- and under-design of circuits. Design robustness is improved by pinpointing areas of the chip most susceptible to variations so that designers can reduce this sensitivity and improve the parametric yield of production chips. PrimeTime VX analyzes systematic or deterministic process variation (die-to-die) as well as random process variation (on-die) in a flexible environment with a large range of features that can easily be introduced into existing design flows. PrimeTime VX allows users to leverage their existing investment in their trusted PrimeTime STA tool infrastructure, flow and knowledge.

Thanks for the info.