DRAM controller design

Hi
ok i am creating a a DRAM controller according to the following specifications, however so things i don't understand. What does it mean by "Also RD and WR signals are “stored”."? Does this mean it is registered?

The inputs to the circuit are a 16 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (EN). This circuit does not function until EN becomes 1, then the 16-bit ADDRIN is loaded in as a row address (15 down to 8.) and a column address ( 7 down to 0) registers. Also RD and WR signals are “stored”. Subsequently, the row address is outputted at ( ADDROUT) along with the row address strobe (RAS) signal which is generated one clock cycle later. Then, the column address is outputted along with the column address strobe signal (CAS), which is generated one clock cycle later. Finally, if the operation is a write operation ( RD = 0, WR = 1), then the WE output is 1.Otherwise for a read operation ( RD = 1, WR = 0), the WE output remains 0. If RD and WR are both 1, then the controller outputs the row address only. The controller returns to the initial state after generating all the required signals.

P.S

Since the RAS and CAS are generated one clock later, I would think that "stored" in this case means the RD and WR signals are stored in registers and pipelined out with their corresponding RAS and CAS. So essentially, since the RAS and CAS are delayed by a clock, you need to delay your RD and WR signals as well.

not sure but frznchckns answer looks logical

Hi,

I would think the specification does mean

you have a one cycle valid input (when En = 1) which may generate a 3 clock cycle output

output cycle 1.) RAS and Address[15:8]
output cycle 2.) CAS and Address[7:0] //this cycle is only if not (RD=1 and WR=1)
output cycle 3.) WE //this cycle is only if not (RD=1 and WR=1)

so to allow a correct output at cycle 3 (even when the input is only valid for one cycle) you need to store the RD/WR signals.

What the specification does not say is how the circuit should behave if the input is EN=1 and RD=0 and WR=0

regards

i assumed that when RD=0 and WR=0 would give the same result as when RD=1 and WR=1.

ok i have done a state diagram for it, tell me what you think of it.
View attachment statemachine.doc

Hi,

I would see the statemachine like this.

regards

but i don't think you included the condition when RD=1 and WR=1?


(edit) i just had a look again you have included it.