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enable signal optimized during synthesis - WHY ?

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rohit_singh1

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Could anybody please tell me why in the code below because of the synthesis directive, the en input is optimized away during synthesis and left as a dangling input ?

Code: 
module code4b (y, a, en);
  output [3:0] y;
  input  [1:0] a;
  input        en;
  reg    [3:0] y;
  always @(a or en) begin
    y = 4'h0;
    case ({en,a}) // synopsys full_case
      3'b1_00: y[a] = 1'b1;
      3'b1_01: y[a] = 1'b1;
      3'b1_10: y[a] = 1'b1;
      3'b1_11: y[a] = 1'b1;
    endcase
  end
endmodule

Any help is appreciated.

TIA
 

You only specify when en = 1, what logic is suppose to do. When en = 0, you leave the decision to the synthesis tool to do what ever it wants to do and you don't care. Synthesis tool can do the following things, for example:

case ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
3'b0_00: y[a] = 1'b1;
3'b0_01: y[a] = 1'b1;
3'b0_10: y[a] = 1'b1;
3'b0_11: y[a] = 1'b1;
endcase

You can see clearly that en becomes irrelevant to the output, and it is not surprising that the signal does not show up in your synthesis netlist.
 
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