Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Checking net delays in PlanAhead Xilinx ISE 12.3

Status
Not open for further replies.
U

upal

Junior Member level 1
Joined
Jan 23, 2011
Messages
16
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,438
Hello,

I am using ISE 12.3 to simulate my design.How can i use PlanAhead to see the net delays.FpgaEditor is not opening because of some problem.Is there any way to see net delays in PlanAhead.



Thanks in advance
 

upal said:
Hello,

I am using ISE 12.3 to simulate my design.How can i use PlanAhead to see the net delays.FpgaEditor is not opening because of some problem.Is there any way to see net delays in PlanAhead.



Thanks in advance
Click to expand...

As for fpga editor not opening. You did not specify, but I'm guessing you're running linux....

Code: 
export DISPLAY=:0

... before starting ise. Possibly you might need some X libs as well, dending on your install.

Also see:

**broken link removed**

**broken link removed**


Hope that helps. :)
 
  • Like
Reactions: upal

    U

    upal

    Points: 2
    Helpful Answer Positive Rating
yeah, there are a few things in linux that mess up fpga_editor. keep in mind that it can take several minutes to load,

you can also use things like trce to get the delays from a routed design. IIRC, you can also get a post-par simulation model as well.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top